147 lines
5.0 KiB
C
147 lines
5.0 KiB
C
/*-
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* Copyright (C) 2012 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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__FBSDID("$FreeBSD$");
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#ifndef __IOAT_HW_H__
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#define __IOAT_HW_H__
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#define IOAT_MAX_CHANNELS 32
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#define IOAT_CHANCNT_OFFSET 0x00
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#define IOAT_XFERCAP_OFFSET 0x01
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/* Only bits [4:0] are valid. */
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#define IOAT_XFERCAP_VALID_MASK 0x1f
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#define IOAT_GENCTRL_OFFSET 0x02
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#define IOAT_INTRCTRL_OFFSET 0x03
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#define IOAT_INTRCTRL_MASTER_INT_EN 0x01
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#define IOAT_ATTNSTATUS_OFFSET 0x04
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#define IOAT_CBVER_OFFSET 0x08
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#define IOAT_INTRDELAY_OFFSET 0x0C
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#define IOAT_INTRDELAY_SUPPORTED (1 << 15)
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/* Reserved. (1 << 14) */
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/* [13:0] is the coalesce period, in microseconds. */
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#define IOAT_INTRDELAY_US_MASK ((1 << 14) - 1)
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#define IOAT_CS_STATUS_OFFSET 0x0E
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#define IOAT_DMACAPABILITY_OFFSET 0x10
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/* DMA Channel Registers */
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#define IOAT_CHANCTRL_OFFSET 0x80
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#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
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#define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200
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#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
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#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
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#define IOAT_CHANCTRL_ERR_INT_EN 0x0010
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#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
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#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
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#define IOAT_CHANCTRL_INT_REARM 0x0001
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#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\
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IOAT_CHANCTRL_ERR_COMPLETION_EN |\
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IOAT_CHANCTRL_ANY_ERR_ABORT_EN |\
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IOAT_CHANCTRL_ERR_INT_EN)
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#define IOAT_CHANCMD_OFFSET 0x84
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#define IOAT_CHANCMD_RESET 0x20
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#define IOAT_CHANCMD_SUSPEND 0x04
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#define IOAT_DMACOUNT_OFFSET 0x86
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#define IOAT_CHANSTS_OFFSET_LOW 0x88
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#define IOAT_CHANSTS_OFFSET_HIGH 0x8C
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#define IOAT_CHANSTS_OFFSET 0x88
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#define IOAT_CHANSTS_STATUS 0x7ULL
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#define IOAT_CHANSTS_ACTIVE 0x0
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#define IOAT_CHANSTS_IDLE 0x1
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#define IOAT_CHANSTS_SUSPENDED 0x2
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#define IOAT_CHANSTS_HALTED 0x3
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#define IOAT_CHANSTS_ARMED 0x4
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#define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL
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#define IOAT_CHANSTS_SOFT_ERROR 0x10ULL
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#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL)
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#define IOAT_CHAINADDR_OFFSET_LOW 0x90
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#define IOAT_CHAINADDR_OFFSET_HIGH 0x94
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#define IOAT_CHANCMP_OFFSET_LOW 0x98
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#define IOAT_CHANCMP_OFFSET_HIGH 0x9C
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#define IOAT_CHANERR_OFFSET 0xA8
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#define IOAT_CHANERR_XSADDERR (1 << 0)
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#define IOAT_CHANERR_XDADDERR (1 << 1)
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#define IOAT_CHANERR_NDADDERR (1 << 2)
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#define IOAT_CHANERR_DERR (1 << 3)
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#define IOAT_CHANERR_CHADDERR (1 << 4)
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#define IOAT_CHANERR_CCMDERR (1 << 5)
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#define IOAT_CHANERR_CUNCORERR (1 << 6)
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#define IOAT_CHANERR_DUNCORERR (1 << 7)
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#define IOAT_CHANERR_RDERR (1 << 8)
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#define IOAT_CHANERR_WDERR (1 << 9)
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#define IOAT_CHANERR_DCERR (1 << 10)
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#define IOAT_CHANERR_DXSERR (1 << 11)
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#define IOAT_CHANERR_CMPADDERR (1 << 12)
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#define IOAT_CHANERR_INTCFGERR (1 << 13)
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#define IOAT_CHANERR_SEDERR (1 << 14)
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#define IOAT_CHANERR_UNAFFERR (1 << 15)
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#define IOAT_CHANERR_CXPERR (1 << 16)
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/* Reserved. (1 << 17) */
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#define IOAT_CHANERR_DCNTERR (1 << 18)
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#define IOAT_CHANERR_DIFFERR (1 << 19)
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#define IOAT_CHANERR_GTVERR (1 << 20)
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#define IOAT_CHANERR_ATVERR (1 << 21)
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#define IOAT_CHANERR_RTVERR (1 << 22)
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#define IOAT_CHANERR_BBERR (1 << 23)
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#define IOAT_CHANERR_RDIFFERR (1 << 24)
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#define IOAT_CHANERR_RGTVERR (1 << 25)
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#define IOAT_CHANERR_RATVERR (1 << 26)
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#define IOAT_CHANERR_RRTVERR (1 << 27)
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#define IOAT_CHANERR_STR \
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"\20\34RRTVERR\33RATVERR\32RGTVERR\31RDIFFERR\30BBERR\27RTVERR\26ATVERR" \
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"\25GTVERR\24DIFFERR\23DCNTERR\21CXPERR\20UNAFFERR\17SEDERR\16INTCFGERR" \
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"\15CMPADDERR\14DXSERR\13DCERR\12WDERR\11RDERR\10DUNCORERR\07CUNCORERR" \
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"\06CCMDERR\05CHADDERR\04DERR\03NDADDERR\02XDADDERR\01XSADDERR"
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#define IOAT_CFG_CHANERR_INT_OFFSET 0x180
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#define IOAT_CFG_CHANERRMASK_INT_OFFSET 0x184
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#define IOAT_MIN_ORDER 4
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#define IOAT_MAX_ORDER 16
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#endif /* __IOAT_HW_H__ */
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