79b96fdbcb
Emulate the 'bit test' instruction. MFC r282259: Re-implement RTC current time calculation to eliminate the possibility of losing time. MFC r282281: Advertise the MTRR feature via CPUID and emulate the minimal set of MTRR MSRs. MFC r282284: When an instruction cannot be decoded just return to userspace so bhyve(8) can dump the instruction bytes. MFC r282287: Don't require <sys/cpuset.h> to be always included before <machine/vmm.h>. MFC r282296: Emulate MSR_SYSCFG which is accessed by Linux on AMD cpus when MTRRs are enabled. MFC r282301: Relax limits when transitioning a vector from the IRR to the ISR and also when extinguishing it from the ISR in response to an EOI. MFC r282335: Advertise an additional memory BAR in the "dummy" device emulation. MFC r282336: Emulate machine check related MSRs to allow guest OSes like Windows to boot. MFC r282351: Don't advertise the Intel SMX capability to the guest. MFC r282407: Emulate the 'CMP r/m8, imm8' instruction. MFC r282519: Add macros for AMD-specific bits in MSR_EFER: LMSLE, FFXSR and TCE. MFC r282520: Emulate guest writes to EFER_MSR properly. MFC r282558: Deprecate the 3-way return values from vm_gla2gpa() and vm_copy_setup(). MFC r282571: Check 'td_owepreempt' and yield the vcpu thread if it is set. MFC r282595: Allow byte reads of AHCI registers. MFC r282784: Handling indirect descriptors is a capability of the host and not one that needs to be negotiated. Use the host capabilities field and not the negotiated field when verifying that indirect descriptors are supported. MFC r282788: Allow configuration of the sector size advertised to the guest. MFC r282865: Set the subvendor field in config space to the vendor ID. This is required by the Windows virtio drivers to correctly match a device. MFC r282922: Bump the size of the blockif scatter-gather list to 67. MFC r283075: Fix off-by-one in array index bounds check. bhyveload would allow you to create 33 entries on an array that only has 32 slots MFC r283168: Temporarily revert r282922 which bumped the max descriptors. MFC r283255: Emulate the "CMP r/m, reg" instruction (opcode 39H). MFC r283256: Add an option "--get-vmcs-exit-inst-length" to display the instruction length of the instruction that caused the VM-exit. MFC r283264: Change the header type of the emulated host-bridge from type 1 to type 0. MFC r283293: Don't rely on the 'VM-exit instruction length' field in the VMCS to always have an accurate length on an EPT violation. MFC r283299: Remove bogus verification of instruction length after instruction decode. MFC r283308: Exceptions don't deliver an error code in real mode. MFC r283657: Fix non-deterministic delays when accessing a vcpu that was in "running" or "sleeping" state. MFC r283973: Use tunable 'hw.vmm.svm.features' to disable specific SVM features even though they might be available in hardware. Use tunable 'hw.vmm.svm.num_asids' to limit the number of ASIDs used by the hypervisor. MFC r284046: Fix regression in 'verify_gla()' with the RIP-relative addressing mode. MFC r284174: Support guest writes to the TSC by enabling the "use TSC offsetting" execution control.
117 lines
4.3 KiB
C
117 lines
4.3 KiB
C
/*-
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* Copyright (c) 2012 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VMM_INSTRUCTION_EMUL_H_
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#define _VMM_INSTRUCTION_EMUL_H_
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#include <sys/mman.h>
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/*
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* Callback functions to read and write memory regions.
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*/
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typedef int (*mem_region_read_t)(void *vm, int cpuid, uint64_t gpa,
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uint64_t *rval, int rsize, void *arg);
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typedef int (*mem_region_write_t)(void *vm, int cpuid, uint64_t gpa,
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uint64_t wval, int wsize, void *arg);
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/*
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* Emulate the decoded 'vie' instruction.
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*
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* The callbacks 'mrr' and 'mrw' emulate reads and writes to the memory region
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* containing 'gpa'. 'mrarg' is an opaque argument that is passed into the
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* callback functions.
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*
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* 'void *vm' should be 'struct vm *' when called from kernel context and
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* 'struct vmctx *' when called from user context.
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* s
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*/
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int vmm_emulate_instruction(void *vm, int cpuid, uint64_t gpa, struct vie *vie,
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struct vm_guest_paging *paging, mem_region_read_t mrr,
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mem_region_write_t mrw, void *mrarg);
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int vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
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uint64_t val, int size);
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/*
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* Returns 1 if an alignment check exception should be injected and 0 otherwise.
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*/
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int vie_alignment_check(int cpl, int operand_size, uint64_t cr0,
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uint64_t rflags, uint64_t gla);
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/* Returns 1 if the 'gla' is not canonical and 0 otherwise. */
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int vie_canonical_check(enum vm_cpu_mode cpu_mode, uint64_t gla);
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uint64_t vie_size2mask(int size);
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int vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
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struct seg_desc *desc, uint64_t off, int length, int addrsize, int prot,
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uint64_t *gla);
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#ifdef _KERNEL
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/*
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* APIs to fetch and decode the instruction from nested page fault handler.
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*
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* 'vie' must be initialized before calling 'vmm_fetch_instruction()'
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*/
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int vmm_fetch_instruction(struct vm *vm, int cpuid,
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struct vm_guest_paging *guest_paging,
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uint64_t rip, int inst_length, struct vie *vie,
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int *is_fault);
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/*
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* Translate the guest linear address 'gla' to a guest physical address.
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*
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* retval is_fault Interpretation
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* 0 0 'gpa' contains result of the translation
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* 0 1 An exception was injected into the guest
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* EFAULT N/A An unrecoverable hypervisor error occurred
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*/
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int vm_gla2gpa(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
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uint64_t gla, int prot, uint64_t *gpa, int *is_fault);
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void vie_init(struct vie *vie, const char *inst_bytes, int inst_length);
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/*
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* Decode the instruction fetched into 'vie' so it can be emulated.
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*
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* 'gla' is the guest linear address provided by the hardware assist
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* that caused the nested page table fault. It is used to verify that
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* the software instruction decoding is in agreement with the hardware.
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*
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* Some hardware assists do not provide the 'gla' to the hypervisor.
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* To skip the 'gla' verification for this or any other reason pass
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* in VIE_INVALID_GLA instead.
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*/
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#define VIE_INVALID_GLA (1UL << 63) /* a non-canonical address */
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int vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla,
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enum vm_cpu_mode cpu_mode, int csd, struct vie *vie);
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#endif /* _KERNEL */
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#endif /* _VMM_INSTRUCTION_EMUL_H_ */
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