8bf1194fe5
Freescale's QorIQ line includes a new ethernet controller, based on their Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame manager, Buffer manager, and Queue manager to improve performance across all interfaces by being able to pass data directly between hardware acceleration interfaces. As part of this import, Freescale's Netcomm Software (ncsw) driver is imported. This was an attempt by Freescale to create an OS-agnostic sub-driver for managing the hardware, using shims to interface to the OS-specific APIs. This work was abandoned, and Freescale's primary work is in the Linux driver (dual BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than going through the vendor area. Going forward, FreeBSD-specific changes may be made to the ncsw code, diverging from the upstream in potentially incompatible ways. An alternative could be to import the Linux driver itself, using the linuxKPI layer, as that would maintain parity with the vendor-maintained driver. However, the Linux driver has not been evaluated for reliability yet, and may have issues with the import, whereas the ncsw-based driver in this commit was completed by Semihalf 4 years ago, and is very stable. Other SoC modules based on DPAA, which could be added in the future: * Security and Encryption engine (SEC4.x, SEC5.x) * RAID engine Additional work to be done: * Implement polling mode * Test vlan support * Add support for the Pattern Matching Engine, which can do regular expression matching on packets. This driver has been tested on the P5020 QorIQ SoC. Others listed in the dtsec(4) manual page are expected to work as the same DPAA engine is included in all. Obtained from: Semihalf Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing
65 lines
2.3 KiB
C
65 lines
2.3 KiB
C
/*-
|
|
* Copyright (C) 2002 Benno Rice.
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
|
|
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
|
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
|
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
|
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
|
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*
|
|
* $FreeBSD$
|
|
*/
|
|
|
|
#ifndef _MACHINE_INTR_MACHDEP_H_
|
|
#define _MACHINE_INTR_MACHDEP_H_
|
|
|
|
#define INTR_VECTORS 256
|
|
|
|
#define MAX_PICS 16
|
|
#define MAP_IRQ(node, pin) powerpc_get_irq(node, pin)
|
|
|
|
/*
|
|
* Default base address for MSI messages on PowerPC
|
|
*/
|
|
#define MSI_INTEL_ADDR_BASE 0xfee00000
|
|
|
|
extern device_t root_pic;
|
|
|
|
struct trapframe;
|
|
|
|
driver_filter_t powerpc_ipi_handler;
|
|
|
|
void intrcnt_add(const char *name, u_long **countp);
|
|
|
|
void powerpc_register_pic(device_t, uint32_t, u_int, u_int, u_int);
|
|
u_int powerpc_get_irq(uint32_t, u_int);
|
|
|
|
void powerpc_dispatch_intr(u_int, struct trapframe *);
|
|
int powerpc_enable_intr(void);
|
|
int powerpc_setup_intr(const char *, u_int, driver_filter_t, driver_intr_t,
|
|
void *, enum intr_type, void **);
|
|
int powerpc_teardown_intr(void *);
|
|
int powerpc_bind_intr(u_int irq, u_char cpu);
|
|
int powerpc_config_intr(int, enum intr_trigger, enum intr_polarity);
|
|
int powerpc_fw_config_intr(int irq, int sense_code);
|
|
|
|
void powerpc_intr_mask(u_int irq);
|
|
void powerpc_intr_unmask(u_int irq);
|
|
|
|
#endif /* _MACHINE_INTR_MACHDEP_H_ */
|