a698b62cf5
served as the basis for too many other platforms).
554 lines
16 KiB
C
554 lines
16 KiB
C
/*-
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* Copyright (c) 2006 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Compact Flash Support for the Avila Gateworks XScale boards.
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* The CF slot is operated in "True IDE" mode. Registers are on
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* the Expansion Bus connected to CS1 and CS2. Interrupts are
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* tied to GPIO pin 12. No DMA, just PIO.
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*
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* The ADI Pronghorn Metro is very similar. It use CS3 and CS4 and
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* GPIO pin 0 for interrupts.
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*
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* See also http://www.intel.com/design/network/applnots/302456.htm.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/time.h>
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#include <sys/bus.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/endian.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <arm/xscale/ixp425/ixp425reg.h>
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#include <arm/xscale/ixp425/ixp425var.h>
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#include <sys/ata.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <dev/ata/ata-all.h>
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#include <ata_if.h>
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#define AVILA_IDE_CTRL 0x06
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struct ata_config {
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const char *desc; /* description for probe */
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uint8_t gpin; /* GPIO pin */
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uint8_t irq; /* IRQ */
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uint32_t base16; /* CS base addr for 16-bit */
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uint32_t size16; /* CS size for 16-bit */
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uint32_t off16; /* CS offset for 16-bit */
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uint32_t basealt; /* CS base addr for alt */
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uint32_t sizealt; /* CS size for alt */
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uint32_t offalt; /* CS offset for alt */
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};
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static const struct ata_config *
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ata_getconfig(struct ixp425_softc *sa)
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{
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static const struct ata_config configs[] = {
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{ .desc = "Gateworks Avila IDE/CF Controller",
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.gpin = 12,
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.irq = IXP425_INT_GPIO_12,
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.base16 = IXP425_EXP_BUS_CS1_HWBASE,
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.size16 = IXP425_EXP_BUS_CS1_SIZE,
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.off16 = EXP_TIMING_CS1_OFFSET,
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.basealt = IXP425_EXP_BUS_CS2_HWBASE,
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.sizealt = IXP425_EXP_BUS_CS2_SIZE,
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.offalt = EXP_TIMING_CS2_OFFSET,
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},
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{ .desc = "Gateworks Cambria IDE/CF Controller",
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.gpin = 12,
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.irq = IXP425_INT_GPIO_12,
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.base16 = CAMBRIA_CFSEL0_HWBASE,
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.size16 = CAMBRIA_CFSEL0_SIZE,
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.off16 = EXP_TIMING_CS3_OFFSET,
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.basealt = CAMBRIA_CFSEL1_HWBASE,
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.sizealt = CAMBRIA_CFSEL1_SIZE,
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.offalt = EXP_TIMING_CS4_OFFSET,
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},
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{ .desc = "ADI Pronghorn Metro IDE/CF Controller",
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.gpin = 0,
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.irq = IXP425_INT_GPIO_0,
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.base16 = IXP425_EXP_BUS_CS3_HWBASE,
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.size16 = IXP425_EXP_BUS_CS3_SIZE,
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.off16 = EXP_TIMING_CS3_OFFSET,
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.basealt = IXP425_EXP_BUS_CS4_HWBASE,
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.sizealt = IXP425_EXP_BUS_CS4_SIZE,
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.offalt = EXP_TIMING_CS4_OFFSET,
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},
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};
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/* XXX honor hint? (but then no multi-board support) */
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/* XXX total hack */
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if (cpu_is_ixp43x())
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return &configs[1]; /* Cambria */
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if (EXP_BUS_READ_4(sa, EXP_TIMING_CS2_OFFSET) != 0)
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return &configs[0]; /* Avila */
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return &configs[2]; /* Pronghorn */
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}
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struct ata_avila_softc {
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device_t sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_exp_ioh; /* Exp Bus config registers */
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bus_space_handle_t sc_ioh; /* CS1/3 data registers */
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bus_space_handle_t sc_alt_ioh; /* CS2/4 data registers */
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struct bus_space sc_expbus_tag;
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struct resource sc_ata; /* hand-crafted for ATA */
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struct resource sc_alt_ata; /* hand-crafted for ATA */
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u_int32_t sc_16bit_off; /* EXP_TIMING_CSx_OFFSET */
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int sc_rid; /* rid for IRQ */
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struct resource *sc_irq; /* IRQ resource */
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void *sc_ih; /* interrupt handler */
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struct {
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void (*cb)(void *);
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void *arg;
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} sc_intr[1]; /* NB: 1/channel */
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};
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static void ata_avila_intr(void *);
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bs_protos(ata);
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static void ata_bs_rm_2_s(void *, bus_space_handle_t, bus_size_t,
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u_int16_t *, bus_size_t);
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static void ata_bs_wm_2_s(void *, bus_space_handle_t, bus_size_t,
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const u_int16_t *, bus_size_t);
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static int
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ata_avila_probe(device_t dev)
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{
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struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
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const struct ata_config *config;
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config = ata_getconfig(sa);
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if (config != NULL) {
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device_set_desc_copy(dev, config->desc);
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return 0;
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}
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return ENXIO;
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}
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static int
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ata_avila_attach(device_t dev)
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{
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struct ata_avila_softc *sc = device_get_softc(dev);
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struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
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const struct ata_config *config;
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config = ata_getconfig(sa);
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KASSERT(config != NULL, ("no board config"));
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sc->sc_dev = dev;
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/* NB: borrow from parent */
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sc->sc_iot = sa->sc_iot;
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sc->sc_exp_ioh = sa->sc_exp_ioh;
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if (bus_space_map(sc->sc_iot, config->base16, config->size16,
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0, &sc->sc_ioh))
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panic("%s: cannot map 16-bit window (0x%x/0x%x)",
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__func__, config->base16, config->size16);
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if (bus_space_map(sc->sc_iot, config->basealt, config->sizealt,
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0, &sc->sc_alt_ioh))
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panic("%s: cannot map alt window (0x%x/0x%x)",
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__func__, config->basealt, config->sizealt);
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sc->sc_16bit_off = config->off16;
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if (config->base16 != CAMBRIA_CFSEL0_HWBASE) {
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/*
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* Craft special resource for ATA bus space ops
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* that go through the expansion bus and require
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* special hackery to ena/dis 16-bit operations.
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*
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* XXX probably should just make this generic for
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* accessing the expansion bus.
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*/
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sc->sc_expbus_tag.bs_cookie = sc; /* NB: backpointer */
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/* read single */
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sc->sc_expbus_tag.bs_r_1 = ata_bs_r_1,
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sc->sc_expbus_tag.bs_r_2 = ata_bs_r_2,
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/* read multiple */
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sc->sc_expbus_tag.bs_rm_2 = ata_bs_rm_2,
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sc->sc_expbus_tag.bs_rm_2_s = ata_bs_rm_2_s,
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/* write (single) */
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sc->sc_expbus_tag.bs_w_1 = ata_bs_w_1,
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sc->sc_expbus_tag.bs_w_2 = ata_bs_w_2,
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/* write multiple */
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sc->sc_expbus_tag.bs_wm_2 = ata_bs_wm_2,
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sc->sc_expbus_tag.bs_wm_2_s = ata_bs_wm_2_s,
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rman_set_bustag(&sc->sc_ata, &sc->sc_expbus_tag);
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rman_set_bustag(&sc->sc_alt_ata, &sc->sc_expbus_tag);
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} else {
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/*
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* On Cambria use the shared CS3 expansion bus tag
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* that handles interlock for sharing access with the
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* optional UART's.
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*/
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rman_set_bustag(&sc->sc_ata, &cambria_exp_bs_tag);
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rman_set_bustag(&sc->sc_alt_ata, &cambria_exp_bs_tag);
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}
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rman_set_bushandle(&sc->sc_ata, sc->sc_ioh);
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rman_set_bushandle(&sc->sc_alt_ata, sc->sc_alt_ioh);
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ixp425_set_gpio(sa, config->gpin, GPIO_TYPE_EDG_RISING);
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/* configure CS1/3 window, leaving timing unchanged */
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EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
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EXP_BUS_READ_4(sc, sc->sc_16bit_off) |
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EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
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/* configure CS2/4 window, leaving timing unchanged */
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EXP_BUS_WRITE_4(sc, config->offalt,
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EXP_BUS_READ_4(sc, config->offalt) |
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EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
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/* setup interrupt */
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sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_rid,
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config->irq, config->irq, 1, RF_ACTIVE);
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if (!sc->sc_irq)
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panic("Unable to allocate irq %u.\n", config->irq);
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bus_setup_intr(dev, sc->sc_irq,
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INTR_TYPE_BIO | INTR_MPSAFE | INTR_ENTROPY,
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NULL, ata_avila_intr, sc, &sc->sc_ih);
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/* attach channel on this controller */
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device_add_child(dev, "ata", -1);
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bus_generic_attach(dev);
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return 0;
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}
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static int
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ata_avila_detach(device_t dev)
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{
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struct ata_avila_softc *sc = device_get_softc(dev);
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/* XXX quiesce gpio? */
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/* detach & delete all children */
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device_delete_children(dev);
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bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
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bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rid, sc->sc_irq);
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return 0;
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}
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static void
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ata_avila_intr(void *xsc)
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{
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struct ata_avila_softc *sc = xsc;
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if (sc->sc_intr[0].cb != NULL)
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sc->sc_intr[0].cb(sc->sc_intr[0].arg);
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}
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static struct resource *
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ata_avila_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct ata_avila_softc *sc = device_get_softc(dev);
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KASSERT(type == SYS_RES_IRQ && *rid == ATA_IRQ_RID,
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("type %u rid %u start %lu end %lu count %lu flags %u",
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type, *rid, start, end, count, flags));
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/* doesn't matter what we return so reuse the real thing */
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return sc->sc_irq;
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}
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static int
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ata_avila_release_resource(device_t dev, device_t child, int type, int rid,
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struct resource *r)
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{
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KASSERT(type == SYS_RES_IRQ && rid == ATA_IRQ_RID,
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("type %u rid %u", type, rid));
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return 0;
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}
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static int
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ata_avila_setup_intr(device_t dev, device_t child, struct resource *irq,
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int flags, driver_filter_t *filt,
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driver_intr_t *function, void *argument, void **cookiep)
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{
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struct ata_avila_softc *sc = device_get_softc(dev);
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int unit = ((struct ata_channel *)device_get_softc(child))->unit;
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KASSERT(unit == 0, ("unit %d", unit));
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sc->sc_intr[unit].cb = function;
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sc->sc_intr[unit].arg = argument;
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*cookiep = sc;
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return 0;
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}
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static int
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ata_avila_teardown_intr(device_t dev, device_t child, struct resource *irq,
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void *cookie)
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{
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struct ata_avila_softc *sc = device_get_softc(dev);
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int unit = ((struct ata_channel *)device_get_softc(child))->unit;
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KASSERT(unit == 0, ("unit %d", unit));
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sc->sc_intr[unit].cb = NULL;
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sc->sc_intr[unit].arg = NULL;
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return 0;
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}
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/*
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* Bus space accessors for CF-IDE PIO operations.
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*/
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/*
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* Enable/disable 16-bit ops on the expansion bus.
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*/
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static __inline void
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enable_16(struct ata_avila_softc *sc)
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{
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EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
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EXP_BUS_READ_4(sc, sc->sc_16bit_off) &~ EXP_BYTE_EN);
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DELAY(100); /* XXX? */
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}
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static __inline void
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disable_16(struct ata_avila_softc *sc)
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{
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DELAY(100); /* XXX? */
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EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
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EXP_BUS_READ_4(sc, sc->sc_16bit_off) | EXP_BYTE_EN);
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}
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uint8_t
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ata_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o)
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{
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struct ata_avila_softc *sc = t;
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return bus_space_read_1(sc->sc_iot, h, o);
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}
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void
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ata_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
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{
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struct ata_avila_softc *sc = t;
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bus_space_write_1(sc->sc_iot, h, o, v);
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}
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uint16_t
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ata_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o)
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{
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struct ata_avila_softc *sc = t;
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uint16_t v;
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enable_16(sc);
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v = bus_space_read_2(sc->sc_iot, h, o);
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disable_16(sc);
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return v;
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}
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void
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ata_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
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{
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struct ata_avila_softc *sc = t;
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enable_16(sc);
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bus_space_write_2(sc->sc_iot, h, o, v);
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disable_16(sc);
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}
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void
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ata_bs_rm_2(void *t, bus_space_handle_t h, bus_size_t o,
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u_int16_t *d, bus_size_t c)
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{
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struct ata_avila_softc *sc = t;
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enable_16(sc);
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bus_space_read_multi_2(sc->sc_iot, h, o, d, c);
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disable_16(sc);
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}
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void
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ata_bs_wm_2(void *t, bus_space_handle_t h, bus_size_t o,
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const u_int16_t *d, bus_size_t c)
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{
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struct ata_avila_softc *sc = t;
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enable_16(sc);
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bus_space_write_multi_2(sc->sc_iot, h, o, d, c);
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disable_16(sc);
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}
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/* XXX workaround ata driver by (incorrectly) byte swapping stream cases */
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void
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ata_bs_rm_2_s(void *t, bus_space_handle_t h, bus_size_t o,
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u_int16_t *d, bus_size_t c)
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{
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struct ata_avila_softc *sc = t;
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uint16_t v;
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bus_size_t i;
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enable_16(sc);
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#if 1
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for (i = 0; i < c; i++) {
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v = bus_space_read_2(sc->sc_iot, h, o);
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d[i] = bswap16(v);
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}
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#else
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bus_space_read_multi_stream_2(sc->sc_iot, h, o, d, c);
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#endif
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disable_16(sc);
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}
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void
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ata_bs_wm_2_s(void *t, bus_space_handle_t h, bus_size_t o,
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const u_int16_t *d, bus_size_t c)
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{
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struct ata_avila_softc *sc = t;
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bus_size_t i;
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enable_16(sc);
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#if 1
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for (i = 0; i < c; i++)
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bus_space_write_2(sc->sc_iot, h, o, bswap16(d[i]));
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#else
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bus_space_write_multi_stream_2(sc->sc_iot, h, o, d, c);
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#endif
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disable_16(sc);
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}
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static device_method_t ata_avila_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, ata_avila_probe),
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|
DEVMETHOD(device_attach, ata_avila_attach),
|
|
DEVMETHOD(device_detach, ata_avila_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
/* bus methods */
|
|
DEVMETHOD(bus_alloc_resource, ata_avila_alloc_resource),
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|
DEVMETHOD(bus_release_resource, ata_avila_release_resource),
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, ata_avila_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, ata_avila_teardown_intr),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
devclass_t ata_avila_devclass;
|
|
|
|
static driver_t ata_avila_driver = {
|
|
"ata_avila",
|
|
ata_avila_methods,
|
|
sizeof(struct ata_avila_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(ata_avila, ixp, ata_avila_driver, ata_avila_devclass, 0, 0);
|
|
MODULE_VERSION(ata_avila, 1);
|
|
MODULE_DEPEND(ata_avila, ata, 1, 1, 1);
|
|
|
|
static int
|
|
avila_channel_probe(device_t dev)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
|
|
ch->unit = 0;
|
|
ch->flags |= ATA_USE_16BIT | ATA_NO_SLAVE;
|
|
device_set_desc_copy(dev, "ATA channel 0");
|
|
|
|
return ata_probe(dev);
|
|
}
|
|
|
|
static int
|
|
avila_channel_attach(device_t dev)
|
|
{
|
|
struct ata_avila_softc *sc = device_get_softc(device_get_parent(dev));
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
int i;
|
|
|
|
for (i = 0; i < ATA_MAX_RES; i++)
|
|
ch->r_io[i].res = &sc->sc_ata;
|
|
|
|
ch->r_io[ATA_DATA].offset = ATA_DATA;
|
|
ch->r_io[ATA_FEATURE].offset = ATA_FEATURE;
|
|
ch->r_io[ATA_COUNT].offset = ATA_COUNT;
|
|
ch->r_io[ATA_SECTOR].offset = ATA_SECTOR;
|
|
ch->r_io[ATA_CYL_LSB].offset = ATA_CYL_LSB;
|
|
ch->r_io[ATA_CYL_MSB].offset = ATA_CYL_MSB;
|
|
ch->r_io[ATA_DRIVE].offset = ATA_DRIVE;
|
|
ch->r_io[ATA_COMMAND].offset = ATA_COMMAND;
|
|
ch->r_io[ATA_ERROR].offset = ATA_FEATURE;
|
|
/* NB: should be used only for ATAPI devices */
|
|
ch->r_io[ATA_IREASON].offset = ATA_COUNT;
|
|
ch->r_io[ATA_STATUS].offset = ATA_COMMAND;
|
|
|
|
/* NB: the control and alt status registers are special */
|
|
ch->r_io[ATA_ALTSTAT].res = &sc->sc_alt_ata;
|
|
ch->r_io[ATA_ALTSTAT].offset = AVILA_IDE_CTRL;
|
|
ch->r_io[ATA_CONTROL].res = &sc->sc_alt_ata;
|
|
ch->r_io[ATA_CONTROL].offset = AVILA_IDE_CTRL;
|
|
|
|
/* NB: by convention this points at the base of registers */
|
|
ch->r_io[ATA_IDX_ADDR].offset = 0;
|
|
|
|
ata_generic_hw(dev);
|
|
return ata_attach(dev);
|
|
}
|
|
|
|
static device_method_t avila_channel_methods[] = {
|
|
/* device interface */
|
|
DEVMETHOD(device_probe, avila_channel_probe),
|
|
DEVMETHOD(device_attach, avila_channel_attach),
|
|
DEVMETHOD(device_detach, ata_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, ata_suspend),
|
|
DEVMETHOD(device_resume, ata_resume),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
driver_t avila_channel_driver = {
|
|
"ata",
|
|
avila_channel_methods,
|
|
sizeof(struct ata_channel),
|
|
};
|
|
DRIVER_MODULE(ata, ata_avila, avila_channel_driver, ata_devclass, 0, 0);
|