549 lines
18 KiB
C
549 lines
18 KiB
C
/*******************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @defgroup group_udma_config UDMA Config
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* @ingroup group_udma_api
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* UDMA Config API
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* @{
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* @file al_hal_udma_config.h
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*
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* @brief C Header file for the Universal DMA HAL driver for configuration APIs
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*
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*/
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#ifndef __AL_HAL_UDMA_CONFIG_H__
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#define __AL_HAL_UDMA_CONFIG_H__
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#include <al_hal_udma.h>
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-ON* */
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/** Scheduling mode */
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enum al_udma_sch_mode {
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STRICT, /* Strict */
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SRR, /* Simple Sound Rubin */
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DWRR /* Deficit Weighted Round Rubin */
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};
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/** AXI configuration */
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struct al_udma_axi_conf {
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uint32_t axi_timeout; /* Timeout for AXI transactions */
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uint8_t arb_promotion; /* arbitration promotion */
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al_bool swap_8_bytes; /* enable 8 bytes swap instead of 4 bytes */
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al_bool swap_s2m_data;
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al_bool swap_s2m_desc;
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al_bool swap_m2s_data;
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al_bool swap_m2s_desc;
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};
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/** UDMA AXI M2S configuration */
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struct al_udma_axi_submaster {
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uint8_t id; /* AXI ID */
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uint8_t cache_type;
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uint8_t burst;
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uint16_t used_ext;
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uint8_t bus_size;
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uint8_t qos;
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uint8_t prot;
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uint8_t max_beats;
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};
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/** UDMA AXI M2S configuration */
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struct al_udma_m2s_axi_conf {
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struct al_udma_axi_submaster comp_write;
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struct al_udma_axi_submaster data_read;
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struct al_udma_axi_submaster desc_read;
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al_bool break_on_max_boundary; /* Data read break on max boundary */
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uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
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uint8_t ostand_max_data_read;
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uint8_t ostand_max_desc_read;
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uint8_t ostand_max_comp_req;
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uint8_t ostand_max_comp_write;
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};
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/** UDMA AXI S2M configuration */
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struct al_udma_s2m_axi_conf {
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struct al_udma_axi_submaster data_write;
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struct al_udma_axi_submaster desc_read;
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struct al_udma_axi_submaster comp_write;
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al_bool break_on_max_boundary; /* Data read break on max boundary */
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uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
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uint8_t ostand_max_data_req;
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uint8_t ostand_max_data_write;
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uint8_t ostand_max_comp_req;
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uint8_t ostand_max_comp_write;
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uint8_t ostand_max_desc_read;
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uint8_t ack_fifo_depth; /* size of the stream application ack fifo */
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};
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/** M2S error logging */
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struct al_udma_err_log {
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uint32_t error_status;
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uint32_t header[4];
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};
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/** M2S max packet size configuration */
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struct al_udma_m2s_pkt_len_conf {
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uint32_t max_pkt_size;
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al_bool encode_64k_as_zero;
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};
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/** M2S Descriptor Prefetch configuration */
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struct al_udma_m2s_desc_pref_conf {
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uint8_t desc_fifo_depth;
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enum al_udma_sch_mode sch_mode; /* Scheduling mode
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* (either strict or RR) */
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uint8_t max_desc_per_packet; /* max number of descriptors to
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* prefetch */
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/* in one burst (5b) */
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uint8_t pref_thr;
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uint8_t min_burst_above_thr; /* min burst size when fifo above
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* pref_thr (4b)
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*/
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uint8_t min_burst_below_thr; /* min burst size when fifo below
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* pref_thr (4b)
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*/
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uint8_t max_pkt_limit; /* maximum number of packets in the data
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* read FIFO, defined based on header
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* FIFO size
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*/
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uint16_t data_fifo_depth; /* maximum number of data beats in the
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* data read FIFO,
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* defined based on header FIFO size
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*/
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};
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/** S2M Descriptor Prefetch configuration */
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struct al_udma_s2m_desc_pref_conf {
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uint8_t desc_fifo_depth;
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enum al_udma_sch_mode sch_mode; /* Scheduling mode *
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* (either strict or RR)
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*/
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al_bool q_promotion; /* enable promotion */
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al_bool force_promotion; /* force promotion */
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al_bool en_pref_prediction; /* enable prefetch prediction */
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uint8_t promotion_th; /* Threshold for queue promotion */
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uint8_t pref_thr;
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uint8_t min_burst_above_thr; /* min burst size when fifo above
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* pref_thr (4b)
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*/
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uint8_t min_burst_below_thr; /* min burst size when fifo below
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* pref_thr (4b)
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*/
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uint8_t a_full_thr; /* almost full threshold */
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};
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/** S2M Data write configuration */
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struct al_udma_s2m_data_write_conf {
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uint16_t data_fifo_depth; /* maximum number of data beats in the
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* data write FIFO, defined based on
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* header FIFO size
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*/
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uint8_t max_pkt_limit; /* maximum number of packets in the
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* data write FIFO,defined based on
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* header FIFO size
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*/
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uint8_t fifo_margin;
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uint32_t desc_wait_timer; /* waiting time for the host to write
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* new descriptor to the queue
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* (for the current packet in process)
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*/
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uint32_t flags; /* bitwise of flags of s2m
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* data_cfg_2 register
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*/
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};
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/** S2M Completion configuration */
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struct al_udma_s2m_completion_conf {
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uint8_t desc_size; /* Size of completion descriptor
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* in words
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*/
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al_bool cnt_words; /* Completion fifo in use counter:
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* AL_TRUE words, AL_FALS descriptors
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*/
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al_bool q_promotion; /* Enable promotion of the current
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* unack in progress */
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/* in the completion write scheduler */
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al_bool force_rr; /* force RR arbitration in the
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* scheduler
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*/
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// uint8_t ack_fifo_depth; /* size of the stream application ack fifo */
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uint8_t q_free_min; /* minimum number of free completion
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* entries
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*/
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/* to qualify for promotion */
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uint16_t comp_fifo_depth; /* Size of completion fifo in words */
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uint16_t unack_fifo_depth; /* Size of unacked fifo in descs */
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uint32_t timeout; /* Ack timout from stream interface */
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};
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/** M2S UDMA DWRR configuration */
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struct al_udma_m2s_dwrr_conf {
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al_bool enable_dwrr;
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uint8_t inc_factor;
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uint8_t weight;
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al_bool pkt_mode;
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uint32_t deficit_init_val;
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};
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/** M2S DMA Rate Limitation mode */
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struct al_udma_m2s_rlimit_mode {
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al_bool pkt_mode_en;
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uint16_t short_cycle_sz;
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uint32_t token_init_val;
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};
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/** M2S Stream/Q Rate Limitation */
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struct al_udma_m2s_rlimit_cfg {
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uint32_t max_burst_sz; /* maximum number of accumulated bytes in the
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* token counter
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*/
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uint16_t long_cycle_sz; /* number of short cycles between token fill */
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uint32_t long_cycle; /* number of bits to add in each long cycle */
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uint32_t short_cycle; /* number of bits to add in each cycle */
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uint32_t mask; /* mask the different types of rate limiters */
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};
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enum al_udma_m2s_rlimit_action {
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AL_UDMA_STRM_RLIMIT_ENABLE,
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AL_UDMA_STRM_RLIMIT_PAUSE,
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AL_UDMA_STRM_RLIMIT_RESET
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};
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/** M2S UDMA Q scheduling configuration */
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struct al_udma_m2s_q_dwrr_conf {
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uint32_t max_deficit_cnt_sz; /*maximum number of accumulated bytes
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* in the deficit counter
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*/
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al_bool strict; /* bypass DWRR */
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uint8_t axi_qos;
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uint16_t q_qos;
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uint8_t weight;
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};
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/** M2S UDMA / UDMA Q scheduling configuration */
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struct al_udma_m2s_sc {
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enum al_udma_sch_mode sch_mode; /* Scheduling Mode */
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struct al_udma_m2s_dwrr_conf dwrr; /* DWRR configuration */
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};
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/** UDMA / UDMA Q rate limitation configuration */
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struct al_udma_m2s_rlimit {
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struct al_udma_m2s_rlimit_mode rlimit_mode;
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/* rate limitation enablers */
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#if 0
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struct al_udma_tkn_bkt_conf token_bkt; /* Token Bucket configuration */
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#endif
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};
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/** UDMA Data read configuration */
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struct al_udma_m2s_data_rd_conf {
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uint8_t max_rd_d_beats; /* max burst size for reading data
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* (in AXI beats-128b) (5b)
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*/
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uint8_t max_rd_d_out_req; /* max number of outstanding data
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* read requests (6b)
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*/
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uint16_t max_rd_d_out_beats; /* max num. of data read beats (10b) */
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};
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/** M2S UDMA completion and application timeouts */
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struct al_udma_m2s_comp_timeouts {
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enum al_udma_sch_mode sch_mode; /* Scheduling mode
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* (either strict or RR)
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*/
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al_bool enable_q_promotion;
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uint8_t unack_fifo_depth; /* unacked desc fifo size */
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uint8_t comp_fifo_depth; /* desc fifo size */
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uint32_t coal_timeout; /* (24b) */
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uint32_t app_timeout; /* (24b) */
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};
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/** S2M UDMA per queue completion configuration */
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struct al_udma_s2m_q_comp_conf {
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al_bool dis_comp_coal; /* disable completion coalescing */
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al_bool en_comp_ring_update; /* enable writing completion descs */
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uint32_t comp_timer; /* completion coalescing timer */
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al_bool en_hdr_split; /* enable header split */
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al_bool force_hdr_split; /* force header split */
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uint16_t hdr_split_size; /* size used for the header split */
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uint8_t q_qos; /* queue QoS */
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};
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/** UDMA per queue Target-ID control configuration */
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struct al_udma_gen_tgtid_q_conf {
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/* Enable usage of the Target-ID per queue according to 'tgtid' */
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al_bool queue_en;
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/* Enable usage of the Target-ID from the descriptor buffer address 63:48 */
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al_bool desc_en;
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/* Target-ID to be applied when 'queue_en' is asserted */
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uint16_t tgtid;
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/* TGTADDR to be applied to msbs when 'desc_en' is asserted.
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* Relevant for revisions >= AL_UDMA_REV_ID_REV2 */
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uint16_t tgtaddr;
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};
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/** UDMA Target-ID control configuration */
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struct al_udma_gen_tgtid_conf {
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/* TX queue configuration */
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struct al_udma_gen_tgtid_q_conf tx_q_conf[DMA_MAX_Q];
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/* RX queue configuration */
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struct al_udma_gen_tgtid_q_conf rx_q_conf[DMA_MAX_Q];
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};
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/** UDMA Target-ID MSIX control configuration */
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struct al_udma_gen_tgtid_msix_conf {
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/* Enable write to all TGTID_n registers in the MSI-X Controller */
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al_bool access_en;
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/* use TGTID_n [7:0] from MSI-X Controller for MSI-X message */
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al_bool sel;
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};
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/* Report Error - to be used for abort */
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void al_udma_err_report(struct al_udma *udma);
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/* Statistics - TBD */
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void al_udma_stats_get(struct al_udma *udma);
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/* Misc configurations */
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/* Configure AXI configuration */
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int al_udma_axi_set(struct udma_gen_axi *axi_regs,
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struct al_udma_axi_conf *axi);
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/* Configure UDMA AXI M2S configuration */
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int al_udma_m2s_axi_set(struct al_udma *udma,
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struct al_udma_m2s_axi_conf *axi_m2s);
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/* Configure UDMA AXI S2M configuration */
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int al_udma_s2m_axi_set(struct al_udma *udma,
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struct al_udma_s2m_axi_conf *axi_s2m);
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/* Configure M2S packet len */
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int al_udma_m2s_packet_size_cfg_set(struct al_udma *udma,
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struct al_udma_m2s_pkt_len_conf *conf);
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/* Configure M2S UDMA descriptor prefetch */
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int al_udma_m2s_pref_set(struct al_udma *udma,
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struct al_udma_m2s_desc_pref_conf *conf);
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int al_udma_m2s_pref_get(struct al_udma *udma,
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struct al_udma_m2s_desc_pref_conf *conf);
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/* set m2s packet's max descriptors (including meta descriptors) */
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#define AL_UDMA_M2S_MAX_ALLOWED_DESCS_PER_PACKET 31
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int al_udma_m2s_max_descs_set(struct al_udma *udma, uint8_t max_descs);
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/* set s2m packets' max descriptors */
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#define AL_UDMA_S2M_MAX_ALLOWED_DESCS_PER_PACKET 31
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int al_udma_s2m_max_descs_set(struct al_udma *udma, uint8_t max_descs);
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/* Configure S2M UDMA descriptor prefetch */
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int al_udma_s2m_pref_set(struct al_udma *udma,
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struct al_udma_s2m_desc_pref_conf *conf);
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int al_udma_m2s_pref_get(struct al_udma *udma,
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struct al_udma_m2s_desc_pref_conf *conf);
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/* Configure S2M UDMA data write */
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int al_udma_s2m_data_write_set(struct al_udma *udma,
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struct al_udma_s2m_data_write_conf *conf);
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/* Configure the s2m full line write feature */
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int al_udma_s2m_full_line_write_set(struct al_udma *umda, al_bool enable);
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/* Configure S2M UDMA completion */
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int al_udma_s2m_completion_set(struct al_udma *udma,
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struct al_udma_s2m_completion_conf *conf);
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/* Configure the M2S UDMA scheduling mode */
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int al_udma_m2s_sc_set(struct al_udma *udma,
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struct al_udma_m2s_dwrr_conf *sched);
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/* Configure the M2S UDMA rate limitation */
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int al_udma_m2s_rlimit_set(struct al_udma *udma,
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struct al_udma_m2s_rlimit_mode *mode);
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int al_udma_m2s_rlimit_reset(struct al_udma *udma);
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/* Configure the M2S Stream rate limitation */
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int al_udma_m2s_strm_rlimit_set(struct al_udma *udma,
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struct al_udma_m2s_rlimit_cfg *conf);
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int al_udma_m2s_strm_rlimit_act(struct al_udma *udma,
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enum al_udma_m2s_rlimit_action act);
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/* Configure the M2S UDMA Q rate limitation */
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int al_udma_m2s_q_rlimit_set(struct al_udma_q *udma_q,
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struct al_udma_m2s_rlimit_cfg *conf);
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int al_udma_m2s_q_rlimit_act(struct al_udma_q *udma_q,
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enum al_udma_m2s_rlimit_action act);
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/* Configure the M2S UDMA Q scheduling mode */
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int al_udma_m2s_q_sc_set(struct al_udma_q *udma_q,
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struct al_udma_m2s_q_dwrr_conf *conf);
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int al_udma_m2s_q_sc_pause(struct al_udma_q *udma_q, al_bool set);
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int al_udma_m2s_q_sc_reset(struct al_udma_q *udma_q);
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/* M2S UDMA completion and application timeouts */
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int al_udma_m2s_comp_timeouts_set(struct al_udma *udma,
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struct al_udma_m2s_comp_timeouts *conf);
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int al_udma_m2s_comp_timeouts_get(struct al_udma *udma,
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struct al_udma_m2s_comp_timeouts *conf);
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/* UDMA get revision */
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static INLINE unsigned int al_udma_get_revision(struct unit_regs __iomem *unit_regs)
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{
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return (al_reg_read32(&unit_regs->gen.dma_misc.revision)
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& UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_MASK) >>
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UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_SHIFT;
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}
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/**
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* S2M UDMA Configure the expected behavior of Rx/S2M UDMA when there are no Rx Descriptors.
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*
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* @param udma
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* @param drop_packet when set to true, the UDMA will drop packet.
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* @param gen_interrupt when set to true, the UDMA will generate
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* no_desc_hint interrupt when a packet received and the UDMA
|
|
* doesn't find enough free descriptors for it.
|
|
* @param wait_for_desc_timeout timeout in SB cycles to wait for new
|
|
* descriptors before dropping the packets.
|
|
* Notes:
|
|
* - The hint interrupt is raised immediately without waiting
|
|
* for new descs.
|
|
* - value 0 means wait for ever.
|
|
*
|
|
* Notes:
|
|
* - When get_interrupt is set, the API won't program the iofic to unmask this
|
|
* interrupt, in this case the callee should take care for doing that unmask
|
|
* using the al_udma_iofic_config() API.
|
|
*
|
|
* - The hardware's default configuration is: no drop packet, generate hint
|
|
* interrupt.
|
|
* - This API must be called once and before enabling the UDMA
|
|
*
|
|
* @return 0 if no error found.
|
|
*/
|
|
int al_udma_s2m_no_desc_cfg_set(struct al_udma *udma, al_bool drop_packet, al_bool gen_interrupt, uint32_t wait_for_desc_timeout);
|
|
|
|
/**
|
|
* S2M UDMA configure a queue's completion update
|
|
*
|
|
* @param q_udma
|
|
* @param enable set to true to enable completion update
|
|
*
|
|
* completion update better be disabled for tx queues as those descriptors
|
|
* doesn't carry useful information, thus disabling it saves DMA accesses.
|
|
*
|
|
* @return 0 if no error found.
|
|
*/
|
|
int al_udma_s2m_q_compl_updade_config(struct al_udma_q *udma_q, al_bool enable);
|
|
|
|
/**
|
|
* S2M UDMA configure a queue's completion descriptors coalescing
|
|
*
|
|
* @param q_udma
|
|
* @param enable set to true to enable completion coalescing
|
|
* @param coal_timeout in South Bridge cycles.
|
|
*
|
|
* @return 0 if no error found.
|
|
*/
|
|
int al_udma_s2m_q_compl_coal_config(struct al_udma_q *udma_q, al_bool enable, uint32_t coal_timeout);
|
|
|
|
/**
|
|
* S2M UDMA configure completion descriptors write burst parameters
|
|
*
|
|
* @param udma
|
|
* @param burst_size completion descriptors write burst size in bytes.
|
|
*
|
|
* @return 0 if no error found.
|
|
*/int al_udma_s2m_compl_desc_burst_config(struct al_udma *udma, uint16_t
|
|
burst_size);
|
|
|
|
/**
|
|
* S2M UDMA configure a queue's completion header split
|
|
*
|
|
* @param q_udma
|
|
* @param enable set to true to enable completion header split
|
|
* @param force_hdr_split the header split length will be taken from the queue configuration
|
|
* @param hdr_len header split length.
|
|
*
|
|
* @return 0 if no error found.
|
|
*/
|
|
int al_udma_s2m_q_compl_hdr_split_config(struct al_udma_q *udma_q,
|
|
al_bool enable,
|
|
al_bool force_hdr_split,
|
|
uint32_t hdr_len);
|
|
|
|
/* S2M UDMA per queue completion configuration */
|
|
int al_udma_s2m_q_comp_set(struct al_udma_q *udma_q,
|
|
struct al_udma_s2m_q_comp_conf *conf);
|
|
|
|
/** UDMA Target-ID control configuration per queue */
|
|
void al_udma_gen_tgtid_conf_queue_set(
|
|
struct unit_regs *unit_regs,
|
|
struct al_udma_gen_tgtid_conf *conf,
|
|
uint32_t qid);
|
|
|
|
/** UDMA Target-ID control configuration */
|
|
void al_udma_gen_tgtid_conf_set(
|
|
struct unit_regs __iomem *unit_regs,
|
|
struct al_udma_gen_tgtid_conf *conf);
|
|
|
|
/** UDMA Target-ID MSIX control configuration */
|
|
void al_udma_gen_tgtid_msix_conf_set(
|
|
struct unit_regs __iomem *unit_regs,
|
|
struct al_udma_gen_tgtid_msix_conf *conf);
|
|
|
|
/* *INDENT-OFF* */
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
/* *INDENT-ON* */
|
|
/** @} end of UDMA config group */
|
|
#endif /* __AL_HAL_UDMA_CONFIG_H__ */
|