84 lines
3.1 KiB
C
84 lines
3.1 KiB
C
/*
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* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_UART_DEV_SA1110_H_
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#define _DEV_UART_DEV_SA1110_H_
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#define SACOM_FREQ (3686400 / 16)
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#define SACOMSPEED(b) (SACOM_FREQ / (b) - 1)
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/* UART control register 0 */
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#define SACOM_CR0 0x00
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#define CR0_PE 0x01 /* Parity enable */
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#define CR0_OES 0x02 /* Odd/even parity select */
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#define CR0_SBS 0x04 /* Stop bit select */
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#define CR0_DSS 0x08 /* Data size select */
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#define CR0_SCE 0x10 /* Sample clock enable */
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#define CR0_RCE 0x20 /* Receive clock edge enable */
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#define CR0_TCE 0x40 /* Transmit clock edge enable */
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/* UART control register 1 and 2 - baud rate divisor */
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#define SACOM_CR1 0x04
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#define SACOM_CR2 0x08
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/* UART control register 3 */
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#define SACOM_CR3 0x0C
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#define CR3_RXE 0x01 /* Receiver enable */
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#define CR3_TXE 0x02 /* Transmitter enable */
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#define CR3_BRK 0x04 /* Break */
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#define CR3_RIE 0x08 /* Receive FIFO interrupt enable */
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#define CR3_TIE 0x10 /* Transmit FIFO interrupt enable */
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#define CR3_LBM 0x20 /* Loopback mode */
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/* UART data register */
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#define SACOM_DR 0x14
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#define DR_PRE 0x100 /* Parity error */
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#define DR_FRE 0x200 /* Framing error */
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#define DR_ROR 0x400 /* Receiver overrun */
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/* UART status register 0 */
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#define SACOM_SR0 0x1C
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#define SR0_TFS 0x01 /* Transmit FIFO service request */
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#define SR0_RFS 0x02 /* Receive FIFO service request */
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#define SR0_RID 0x04 /* Receiver idle */
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#define SR0_RBB 0x08 /* Receiver begin of break */
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#define SR0_REB 0x10 /* Receiver end of break */
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#define SR0_EIF 0x20 /* Error in FIFO */
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/* UART status register 1 */
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#define SACOM_SR1 0x20
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#define SR1_TBY 0x01 /* Transmitter busy */
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#define SR1_RNE 0x02 /* Receive FIFO not empty */
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#define SR1_TNF 0x04 /* Transmit FIFO not full */
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#define SR1_PRE 0x08 /* Parity error */
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#define SR1_FRE 0x10 /* Framing error */
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#define SR1_ROR 0x20 /* Receive FIFO overrun */
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#define ISSET(a, b) ((a) & (b))
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#endif
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