71347eff19
The existing API only exposes 'seglen' (the current buffer (segment) length)
with the data buffer pointer set in 'ds_data'. This is fine for the legacy
DMA engine but it won't work for the EDMA engines.
The EDMA engine has a significantly different TX descriptor layout.
* The legacy DMA engine had a ds_data pointer at the same offset in the
descriptor for both TX and RX buffers;
* The EDMA engine has no ds_data for RX - the data is DMAed after the
descriptor;
* The EDMA engine has support for 4 TX buffer/segment pairs in the TX
DMA descriptor;
* The EDMA TX completion is in a different FIFO, and the driver will
'link' the status completion entry to a QCU by a "QCU ID".
I don't know why it's just not filled in by the hardware, alas.
So given that, here are the changes:
* Instead of directly fondling 'ds_data' in ath_desc, change the
ath_hal_filltxdesc() to take an array of buffer pointers as well
as segment len pointers;
* The EDMA TX completion status wants a descriptor and queue id.
This (for now) uses bf_state.bfs_txq and will extract the hardware QCU
ID from that.
* .. and this is ugly and wasteful; it should change to just store
the QCU in the bf_state and save 3/7 bytes in the process.
Now, the weird crap:
* The aggregate TX path was using bf_state->bfs_txq for the TXQ, rather than
taking a function argument. I've tidied that up.
* The multicast queue frames get put on a software TXQ and then that is
appended to the hardware CABQ when appropriate. So for now, make sure
that bf_state->bfs_txq points at the CABQ when adding frames to the
multicast queue.
* .. but the multicast queue TX path for now doesn't use the software
queue and instead
(a) directly sets up the descriptor contents at that point;
(b) the frames on the vap->avp_mcastq are then just appended wholesale
to the CABQ.
So for now, I don't have to worry about making the multicast path
work with aggregation or the per-TID software queue. Phew.
What's left to do:
* I need to modify the 11n ath_hal_chaintxdesc() API to do the same.
I'll do that in a subsequent commit.
* Remove bf_state.bfs_txq entirely and store the QCU as appropriate.
* .. then do the runtime "is this going on the right HWQ?" checks using
that, rather than comparing pointer values.
Tested on:
* AR9280 STA/AP
* AR5416 STA/AP
140 lines
4.8 KiB
C
140 lines
4.8 KiB
C
/*-
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _ATH_AH_OSDEP_H_
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#define _ATH_AH_OSDEP_H_
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/*
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* Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <sys/linker_set.h>
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#include <machine/bus.h>
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/*
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* Bus i/o type definitions.
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*/
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typedef void *HAL_SOFTC;
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typedef bus_space_tag_t HAL_BUS_TAG;
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typedef bus_space_handle_t HAL_BUS_HANDLE;
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/*
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* Although the underlying hardware may support 64 bit DMA, the
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* current Atheros hardware only supports 32 bit addressing.
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*/
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typedef uint32_t HAL_DMA_ADDR;
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/*
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* Linker set writearounds for chip and RF backend registration.
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*/
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#define OS_DATA_SET(set, item) DATA_SET(set, item)
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#define OS_SET_DECLARE(set, ptype) SET_DECLARE(set, ptype)
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#define OS_SET_FOREACH(pvar, set) SET_FOREACH(pvar, set)
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/*
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* Delay n microseconds.
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*/
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#define OS_DELAY(_n) DELAY(_n)
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#define OS_INLINE __inline
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#define OS_MEMZERO(_a, _n) bzero((_a), (_n))
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#define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n)
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#define OS_MEMCMP(_a, _b, _l) memcmp((_a), (_b), (_l))
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#define abs(_a) __builtin_abs(_a)
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struct ath_hal;
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/*
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* The hardware registers are native little-endian byte order.
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* Big-endian hosts are handled by enabling hardware byte-swap
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* of register reads and writes at reset. But the PCI clock
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* domain registers are not byte swapped! Thus, on big-endian
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* platforms we have to explicitly byte-swap those registers.
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* OS_REG_UNSWAPPED identifies the registers that need special handling.
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*
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* This is not currently used by the FreeBSD HAL osdep code; the HAL
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* currently does not configure hardware byteswapping for register space
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* accesses and instead does it through the FreeBSD bus space code.
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*/
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#if _BYTE_ORDER == _BIG_ENDIAN
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#define OS_REG_UNSWAPPED(_reg) \
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(((_reg) >= 0x4000 && (_reg) < 0x5000) || \
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((_reg) >= 0x7000 && (_reg) < 0x8000))
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#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
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#define OS_REG_UNSWAPPED(_reg) (0)
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#endif /* _BYTE_ORDER */
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/*
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* For USB/SDIO support (where access latencies are quite high);
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* some write accesses may be buffered and then flushed when
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* either a read is done, or an explicit flush is done.
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*
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* These are simply placeholders for now.
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*/
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#define OS_REG_WRITE_BUFFER_ENABLE(_ah) \
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do { } while (0)
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#define OS_REG_WRITE_BUFFER_DISABLE(_ah) \
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do { } while (0)
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#define OS_REG_WRITE_BUFFER_FLUSH(_ah) \
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do { } while (0)
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/*
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* Register read/write operations are either handled through
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* platform-dependent routines (or when debugging is enabled
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* with AH_DEBUG); or they are inline expanded using the macros
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* defined below.
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*/
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#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
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#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
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#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
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extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
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extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
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#else
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#define OS_REG_WRITE(_ah, _reg, _val) \
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bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val))
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#define OS_REG_READ(_ah, _reg) \
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bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg))
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#endif
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#ifdef AH_DEBUG_ALQ
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extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
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#else
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#define OS_MARK(_ah, _id, _v)
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#endif
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#endif /* _ATH_AH_OSDEP_H_ */
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