cem 6659d8ab68 Drop CACHE_LINE_SIZE to 64 bytes on x86 ... The actual cache line size has always been 64 bytes. The 128 number arose as an optimization for Core 2 era Intel processors. By default (configurable in BIOS), these CPUs would prefetch adjacent cache lines unintelligently. Newer CPUs prefetch more intelligently. The latest Core 2 era CPU was introduced in September 2008 (Xeon 7400 series, "Dunnington"). If you are still using one of these CPUs, especially in a multi-socket configuration, consider locating the "adjacent cache line prefetch" option in BIOS and disabling it. Reported by: mjg Reviewed by: np Discussed with: jhb Sponsored by: Dell EMC Isilon		2017-08-28 22:28:41 +00:00
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acpica	If x86 CPU implementation of the MWAIT instruction reasonably	2015-05-09 12:28:48 +00:00
bios	Remove Micro Channel Architecture support. Of the commonly available	2017-02-15 23:04:25 +00:00
cloudabi32	Move struct syscall_args syscall arguments parameters container into	2017-06-12 21:03:23 +00:00
conf	Garbage collect kernel option TWA_FLASH_FIRMWARE	2017-07-03 19:33:50 +00:00
i386	MFamd64 r322720, r322723:	2017-08-26 18:12:25 +00:00
ibcs2	Remove register keyword from sys/ and ANSIfy prototypes	2017-05-17 00:34:34 +00:00
include	Drop CACHE_LINE_SIZE to 64 bytes on x86	2017-08-28 22:28:41 +00:00
isa	Fix indent.	2017-06-24 10:19:06 +00:00
linux	Avoid using [LINUX_]SHAREDPAGE constant directly in the vdso code.	2017-07-30 21:24:20 +00:00
pci	Remove pc98 support completely.	2017-01-28 02:22:15 +00:00
xbox
Makefile