a99cc79448
that it can connect to switches at speeds other than 1gb. This requires changing the reference clock speed. Since we still don't have a general clock API that lets a SoC-independant driver manipulate its own clocks, this change includes a weak reference to a routine named cgem_set_ref_clk(). The default implementation is a no-op; SoC-specific code can provide an implementation that actually changes the speed. Submitted by: Thomas Skibo <ThomasSkibo@sbcglobal.net> |
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|---|---|---|
| .. | ||
| zedboard | ||
| files.zynq7 | ||
| std.zynq7 | ||
| uart_dev_cdnc.c | ||
| zy7_bus_space.c | ||
| zy7_devcfg.c | ||
| zy7_ehci.c | ||
| zy7_gpio.c | ||
| zy7_l2cache.c | ||
| zy7_machdep.c | ||
| zy7_mp.c | ||
| zy7_reg.h | ||
| zy7_slcr.c | ||
| zy7_slcr.h | ||