235 lines
7.4 KiB
C
235 lines
7.4 KiB
C
/*-
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* local prototypes */
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static int ata_ite_chipinit(device_t dev);
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static int ata_ite_ch_attach(device_t dev);
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static int ata_ite_821x_setmode(device_t dev, int target, int mode);
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static int ata_ite_8213_setmode(device_t dev, int target, int mode);
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/*
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* Integrated Technology Express Inc. (ITE) chipset support functions
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*/
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static int
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ata_ite_probe(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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static struct ata_chip_id ids[] =
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{{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" },
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{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
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{ ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
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{ 0, 0, 0, 0, 0, 0}};
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if (pci_get_vendor(dev) != ATA_ITE_ID)
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return ENXIO;
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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ata_set_desc(dev);
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ctlr->chipinit = ata_ite_chipinit;
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ata_ite_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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if (ctlr->chip->chipid == ATA_IT8213F) {
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/* the ITE 8213F only has one channel */
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ctlr->channels = 1;
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ctlr->setmode = ata_ite_8213_setmode;
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}
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else {
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/* set PCI mode and 66Mhz reference clock */
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pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
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/* set default active & recover timings */
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pci_write_config(dev, 0x54, 0x31, 1);
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pci_write_config(dev, 0x56, 0x31, 1);
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ctlr->setmode = ata_ite_821x_setmode;
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/* No timing restrictions initally. */
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ctlr->chipset_data = (void *)0;
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}
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ctlr->ch_attach = ata_ite_ch_attach;
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return 0;
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}
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static int
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ata_ite_ch_attach(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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int error;
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error = ata_pci_ch_attach(dev);
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ch->flags |= ATA_CHECKS_CABLE;
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return (error);
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}
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static int
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ata_ite_821x_setmode(device_t dev, int target, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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int devno = (ch->unit << 1) + target;
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int piomode;
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uint8_t *timings = (uint8_t*)(&ctlr->chipset_data);
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u_int8_t udmatiming[] =
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{ 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
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u_int8_t chtiming[] =
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{ 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
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mode = min(mode, ctlr->chip->max_dma);
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/* check the CBLID bits for 80 conductor cable detection */
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if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
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(pci_read_config(parent, 0x40, 2) &
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(ch->unit ? (1<<3) : (1<<2)))) {
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ata_print_cable(dev, "controller");
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mode = ATA_UDMA2;
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}
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if (mode >= ATA_UDMA0) {
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/* enable UDMA mode */
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pci_write_config(parent, 0x50,
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pci_read_config(parent, 0x50, 1) &
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~(1 << (devno + 3)), 1);
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/* set UDMA timing */
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pci_write_config(parent,
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0x56 + (ch->unit << 2) + target,
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udmatiming[mode & ATA_MODE_MASK], 1);
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piomode = ATA_PIO4;
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} else {
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/* disable UDMA mode */
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pci_write_config(parent, 0x50,
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pci_read_config(parent, 0x50, 1) |
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(1 << (devno + 3)), 1);
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piomode = mode;
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}
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timings[devno] = chtiming[ata_mode2idx(piomode)];
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/* set active and recover timing (shared between master & slave) */
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pci_write_config(parent, 0x54 + (ch->unit << 2),
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max(timings[ch->unit << 1], timings[(ch->unit << 1) + 1]), 1);
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return (mode);
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}
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static int
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ata_ite_8213_setmode(device_t dev, int target, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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int piomode;
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u_int16_t reg40 = pci_read_config(parent, 0x40, 2);
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u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
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u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
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u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
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u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
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u_int16_t mask40 = 0, new40 = 0;
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u_int8_t mask44 = 0, new44 = 0;
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u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 };
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u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
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mode = min(mode, ctlr->chip->max_dma);
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if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
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!(reg54 & (0x10 << target))) {
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ata_print_cable(dev, "controller");
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mode = ATA_UDMA2;
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}
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/* Enable/disable UDMA and set timings. */
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if (mode >= ATA_UDMA0) {
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pci_write_config(parent, 0x48, reg48 | (0x0001 << target), 2);
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pci_write_config(parent, 0x4a,
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(reg4a & ~(0x3 << (target << 2))) |
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(utimings[mode & ATA_MODE_MASK] << (target<<2)), 2);
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piomode = ATA_PIO4;
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} else {
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pci_write_config(parent, 0x48, reg48 & ~(0x0001 << target), 2);
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pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (target << 2))),2);
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piomode = mode;
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}
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/* Set UDMA reference clock (33/66/133MHz). */
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reg54 &= ~(0x1001 << target);
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if (mode >= ATA_UDMA5)
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reg54 |= (0x1000 << target);
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else if (mode >= ATA_UDMA3)
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reg54 |= (0x1 << target);
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pci_write_config(parent, 0x54, reg54, 2);
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/* Allow PIO/WDMA timing controls. */
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reg40 &= 0xff00;
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reg40 |= 0x4033;
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/* Set PIO/WDMA timings. */
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if (target == 0) {
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reg40 |= (ata_atapi(dev, target) ? 0x04 : 0x00);
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mask40 = 0x3300;
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new40 = timings[ata_mode2idx(piomode)] << 8;
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}
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else {
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reg40 |= (ata_atapi(dev, target) ? 0x40 : 0x00);
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mask44 = 0x0f;
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new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) |
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(timings[ata_mode2idx(piomode)] & 0x03);
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}
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pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
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pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
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return (mode);
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}
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ATA_DECLARE_DRIVER(ata_ite);
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