np 5b44880756 cxgbe(4): Some more debug sysctls. These work on both T4 and T5 based ...

cards.

dev.t5nex.0.misc.cim_ma_la: CIM MA logic analyzer
dev.t5nex.0.misc.cim_pif_la: CIM PIF logic analyzer
dev.t5nex.0.misc.mps_tcam: MPS TCAM entries
dev.t5nex.0.misc.tp_la: TP logic analyzer
dev.t5nex.0.misc.ulprx_la: ULPRX logic analyzer

Obtained from:	Chelsio
MFC after:	1 week

2013-06-01 02:07:37 +00:00

..

common

cxgbe(4): Some updates to shared code.

2013-04-30 05:32:07 +00:00

firmware

cxgbe(4): Some updates to shared code.

2013-04-30 05:32:07 +00:00

tom

cxgbe/tom: Do not use M_PROTO1 to mark rx zero-copy mbufs as special.

2013-05-03 18:37:50 +00:00

adapter.h

- Provide accurate ifmedia information so that 40G ports/transceivers are

2013-04-30 05:51:52 +00:00

offload.h

cxgbe(4): Updates to the hardware L2 table management code.

2013-01-14 20:36:22 +00:00

osdep.h

cxgbe(4): Some updates to shared code.

2013-04-30 05:32:07 +00:00

t4_ioctl.h

cxgbe(4): Add support for Chelsio's Terminator 5 (aka T5) ASIC. This

2013-03-30 02:26:20 +00:00

t4_l2t.c

cxgbe(4): Updates to the hardware L2 table management code.

2013-01-14 20:36:22 +00:00

t4_l2t.h

cxgbe(4): Updates to the hardware L2 table management code.

2013-01-14 20:36:22 +00:00

t4_main.c

cxgbe(4): Some more debug sysctls. These work on both T4 and T5 based

2013-06-01 02:07:37 +00:00

t4_sge.c

Cosmetic change (s/wrwc/wcwr/;s/WRWC/WCWR/).

2013-04-11 22:49:29 +00:00