5b7a1d2513
The only reason we need to have the sb_load64() and sb_store64() functions in assembly is to cheat the compiler and generate the 'ld' and 'sd' instructions which it otherwise will not do when compiling for a 32-bit architecture. There are some 64-bit registers in the SCD unit that must be accessed using 64-bit load and store instructions.
83 lines
2.6 KiB
ArmAsm
83 lines
2.6 KiB
ArmAsm
/*-
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* Copyright (c) 2009 Neelkanth Natu
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <machine/asm.h>
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/*
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* We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit
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* processor. It has some registers that must be accessed using 64-bit load
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* and store instructions.
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*
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* So we have to resort to assembly because the compiler does not emit the
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* 'ld' and 'sd' instructions since it thinks that it is compiling for a
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* 32-bit mips processor.
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*/
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.set mips64
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.set noat
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.set noreorder
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/*
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* Parameters: uint32_t ptr
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* Return value: *(uint64_t *)ptr
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*/
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LEAF(sb_load64)
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ld v1, 0(a0) /* result = *(uint64_t *)ptr */
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move v0, v1
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#if defined(TARGET_BIG_ENDIAN)
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dsll32 v1, v1, 0
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dsrl32 v1, v1, 0 /* v1 = lower_uint32(result) */
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jr ra
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dsrl32 v0, v0, 0 /* v0 = upper_uint32(result) */
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#else
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dsll32 v0, v0, 0
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dsrl32 v0, v0, 0 /* v0 = lower_uint32(result) */
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jr ra
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dsrl32 v1, v1, 0 /* v1 = upper_uint32(result) */
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#endif
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END(sb_load64)
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/*
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* Parameters: uint32_t ptr, uint64_t val
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* Return value: void
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*/
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LEAF(sb_store64)
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#if defined(TARGET_BIG_ENDIAN)
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dsll32 a2, a2, 0 /* a2 = upper_uint32(val) */
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dsll32 a3, a3, 0 /* a3 = lower_uint32(val) */
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dsrl32 a3, a3, 0
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#else
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dsll32 a3, a3, 0 /* a3 = upper_uint32(val) */
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dsll32 a2, a2, 0 /* a2 = lower_uint32(val) */
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dsrl32 a2, a2, 0
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#endif
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or t0, a2, a3
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jr ra
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sd t0, 0(a0)
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END(sb_store64)
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