56248d9da8
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
329 lines
13 KiB
C
329 lines
13 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-rnm-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon rnm.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_RNM_DEFS_H__
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#define __CVMX_RNM_DEFS_H__
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#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
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#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_RNM_EER_DBG CVMX_RNM_EER_DBG_FUNC()
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static inline uint64_t CVMX_RNM_EER_DBG_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
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cvmx_warn("CVMX_RNM_EER_DBG not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180040000018ull);
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}
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#else
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#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_RNM_EER_KEY CVMX_RNM_EER_KEY_FUNC()
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static inline uint64_t CVMX_RNM_EER_KEY_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
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cvmx_warn("CVMX_RNM_EER_KEY not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180040000010ull);
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}
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#else
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#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_RNM_SERIAL_NUM CVMX_RNM_SERIAL_NUM_FUNC()
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static inline uint64_t CVMX_RNM_SERIAL_NUM_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
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cvmx_warn("CVMX_RNM_SERIAL_NUM not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180040000020ull);
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}
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#else
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#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
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#endif
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/**
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* cvmx_rnm_bist_status
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*
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* RNM_BIST_STATUS = RNM's BIST Status Register
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*
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* The RNM's Memory Bist Status register.
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*/
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union cvmx_rnm_bist_status {
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uint64_t u64;
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struct cvmx_rnm_bist_status_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_2_63 : 62;
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uint64_t rrc : 1; /**< Status of RRC block bist. */
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uint64_t mem : 1; /**< Status of MEM block bist. */
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#else
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uint64_t mem : 1;
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uint64_t rrc : 1;
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uint64_t reserved_2_63 : 62;
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#endif
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} s;
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struct cvmx_rnm_bist_status_s cn30xx;
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struct cvmx_rnm_bist_status_s cn31xx;
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struct cvmx_rnm_bist_status_s cn38xx;
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struct cvmx_rnm_bist_status_s cn38xxp2;
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struct cvmx_rnm_bist_status_s cn50xx;
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struct cvmx_rnm_bist_status_s cn52xx;
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struct cvmx_rnm_bist_status_s cn52xxp1;
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struct cvmx_rnm_bist_status_s cn56xx;
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struct cvmx_rnm_bist_status_s cn56xxp1;
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struct cvmx_rnm_bist_status_s cn58xx;
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struct cvmx_rnm_bist_status_s cn58xxp1;
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struct cvmx_rnm_bist_status_s cn61xx;
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struct cvmx_rnm_bist_status_s cn63xx;
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struct cvmx_rnm_bist_status_s cn63xxp1;
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struct cvmx_rnm_bist_status_s cn66xx;
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struct cvmx_rnm_bist_status_s cn68xx;
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struct cvmx_rnm_bist_status_s cn68xxp1;
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struct cvmx_rnm_bist_status_s cnf71xx;
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};
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typedef union cvmx_rnm_bist_status cvmx_rnm_bist_status_t;
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/**
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* cvmx_rnm_ctl_status
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*
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* RNM_CTL_STATUS = RNM's Control/Status Register
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*
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* The RNM's interrupt enable register.
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*/
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union cvmx_rnm_ctl_status {
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uint64_t u64;
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struct cvmx_rnm_ctl_status_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_12_63 : 52;
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uint64_t dis_mak : 1; /**< Disable use of Master AES KEY */
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uint64_t eer_lck : 1; /**< Encryption enable register locked */
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uint64_t eer_val : 1; /**< Dormant encryption key match */
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uint64_t ent_sel : 4; /**< ? */
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uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */
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uint64_t rng_rst : 1; /**< Reset RNG as core reset. */
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uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register
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logic. */
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uint64_t rng_en : 1; /**< Enable the output of the RNG. */
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uint64_t ent_en : 1; /**< Entropy enable for random number generator. */
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#else
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uint64_t ent_en : 1;
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uint64_t rng_en : 1;
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uint64_t rnm_rst : 1;
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uint64_t rng_rst : 1;
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uint64_t exp_ent : 1;
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uint64_t ent_sel : 4;
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uint64_t eer_val : 1;
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uint64_t eer_lck : 1;
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uint64_t dis_mak : 1;
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uint64_t reserved_12_63 : 52;
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#endif
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} s;
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struct cvmx_rnm_ctl_status_cn30xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_4_63 : 60;
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uint64_t rng_rst : 1; /**< Reset RNG as core reset. */
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uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register
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logic. */
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uint64_t rng_en : 1; /**< Enable the output of the RNG. */
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uint64_t ent_en : 1; /**< Entropy enable for random number generator. */
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#else
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uint64_t ent_en : 1;
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uint64_t rng_en : 1;
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uint64_t rnm_rst : 1;
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uint64_t rng_rst : 1;
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uint64_t reserved_4_63 : 60;
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#endif
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} cn30xx;
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struct cvmx_rnm_ctl_status_cn30xx cn31xx;
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struct cvmx_rnm_ctl_status_cn30xx cn38xx;
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struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
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struct cvmx_rnm_ctl_status_cn50xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_9_63 : 55;
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uint64_t ent_sel : 4; /**< ? */
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uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */
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uint64_t rng_rst : 1; /**< Reset RNG as core reset. */
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uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register
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logic. */
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uint64_t rng_en : 1; /**< Enable the output of the RNG. */
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uint64_t ent_en : 1; /**< Entropy enable for random number generator. */
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#else
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uint64_t ent_en : 1;
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uint64_t rng_en : 1;
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uint64_t rnm_rst : 1;
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uint64_t rng_rst : 1;
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uint64_t exp_ent : 1;
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uint64_t ent_sel : 4;
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uint64_t reserved_9_63 : 55;
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#endif
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} cn50xx;
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struct cvmx_rnm_ctl_status_cn50xx cn52xx;
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struct cvmx_rnm_ctl_status_cn50xx cn52xxp1;
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struct cvmx_rnm_ctl_status_cn50xx cn56xx;
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struct cvmx_rnm_ctl_status_cn50xx cn56xxp1;
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struct cvmx_rnm_ctl_status_cn50xx cn58xx;
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struct cvmx_rnm_ctl_status_cn50xx cn58xxp1;
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struct cvmx_rnm_ctl_status_s cn61xx;
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struct cvmx_rnm_ctl_status_cn63xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_11_63 : 53;
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uint64_t eer_lck : 1; /**< Encryption enable register locked */
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uint64_t eer_val : 1; /**< Dormant encryption key match */
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uint64_t ent_sel : 4; /**< ? */
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uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */
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uint64_t rng_rst : 1; /**< Reset RNG as core reset. */
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uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register
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logic. */
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uint64_t rng_en : 1; /**< Enable the output of the RNG. */
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uint64_t ent_en : 1; /**< Entropy enable for random number generator. */
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#else
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uint64_t ent_en : 1;
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uint64_t rng_en : 1;
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uint64_t rnm_rst : 1;
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uint64_t rng_rst : 1;
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uint64_t exp_ent : 1;
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uint64_t ent_sel : 4;
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uint64_t eer_val : 1;
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uint64_t eer_lck : 1;
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uint64_t reserved_11_63 : 53;
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#endif
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} cn63xx;
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struct cvmx_rnm_ctl_status_cn63xx cn63xxp1;
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struct cvmx_rnm_ctl_status_s cn66xx;
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struct cvmx_rnm_ctl_status_cn63xx cn68xx;
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struct cvmx_rnm_ctl_status_cn63xx cn68xxp1;
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struct cvmx_rnm_ctl_status_s cnf71xx;
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};
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typedef union cvmx_rnm_ctl_status cvmx_rnm_ctl_status_t;
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/**
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* cvmx_rnm_eer_dbg
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*
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* RNM_EER_DBG = RNM's Encryption enable debug register
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*
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* The RNM's Encryption enable debug register
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*/
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union cvmx_rnm_eer_dbg {
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uint64_t u64;
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struct cvmx_rnm_eer_dbg_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t dat : 64; /**< Dormant encryption debug info. */
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#else
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uint64_t dat : 64;
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#endif
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} s;
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struct cvmx_rnm_eer_dbg_s cn61xx;
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struct cvmx_rnm_eer_dbg_s cn63xx;
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struct cvmx_rnm_eer_dbg_s cn63xxp1;
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struct cvmx_rnm_eer_dbg_s cn66xx;
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struct cvmx_rnm_eer_dbg_s cn68xx;
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struct cvmx_rnm_eer_dbg_s cn68xxp1;
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struct cvmx_rnm_eer_dbg_s cnf71xx;
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};
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typedef union cvmx_rnm_eer_dbg cvmx_rnm_eer_dbg_t;
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/**
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* cvmx_rnm_eer_key
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*
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* RNM_EER_KEY = RNM's Encryption enable register
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*
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* The RNM's Encryption enable register
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*/
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union cvmx_rnm_eer_key {
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uint64_t u64;
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struct cvmx_rnm_eer_key_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t key : 64; /**< Dormant encryption key. If dormant crypto is fuse
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enabled, crypto can be enable by writing this
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register with the correct key. */
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#else
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uint64_t key : 64;
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#endif
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} s;
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struct cvmx_rnm_eer_key_s cn61xx;
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struct cvmx_rnm_eer_key_s cn63xx;
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struct cvmx_rnm_eer_key_s cn63xxp1;
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struct cvmx_rnm_eer_key_s cn66xx;
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struct cvmx_rnm_eer_key_s cn68xx;
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struct cvmx_rnm_eer_key_s cn68xxp1;
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struct cvmx_rnm_eer_key_s cnf71xx;
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};
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typedef union cvmx_rnm_eer_key cvmx_rnm_eer_key_t;
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/**
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* cvmx_rnm_serial_num
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*
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* RNM_SERIAL_NUM = RNM's fuse serial number register
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*
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* The RNM's fuse serial number register
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*
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* Notes:
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* Added RNM_SERIAL_NUM in pass 2.0
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*
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*/
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union cvmx_rnm_serial_num {
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uint64_t u64;
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struct cvmx_rnm_serial_num_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t dat : 64; /**< Dormant encryption serial number */
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#else
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uint64_t dat : 64;
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#endif
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} s;
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struct cvmx_rnm_serial_num_s cn61xx;
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struct cvmx_rnm_serial_num_s cn63xx;
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struct cvmx_rnm_serial_num_s cn66xx;
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struct cvmx_rnm_serial_num_s cn68xx;
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struct cvmx_rnm_serial_num_s cn68xxp1;
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struct cvmx_rnm_serial_num_s cnf71xx;
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};
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typedef union cvmx_rnm_serial_num cvmx_rnm_serial_num_t;
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#endif
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