ddcbd7a1c9
The QUICC engine is found on various Freescale parts including MPC85xx, and provides multiple generic time-division serial channel resources, which are in turn muxed/demuxed by the Serial Communications Controller (SCC). Along with core QUICC/SCC functionality a uart(4)-compliant device driver is provided which allows for serial ports over QUICC/SCC. Approved by: cognet (mentor) Obtained from: Juniper MFp4: e500
95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
/*-
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* Copyright (c) 2006 Juniper Networks.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/tty.h>
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#include <machine/bus.h>
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#include <machine/ocpbus.h>
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#include <dev/quicc/quicc_bfe.h>
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static int quicc_ocp_probe(device_t dev);
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static device_method_t quicc_ocp_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, quicc_ocp_probe),
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DEVMETHOD(device_attach, quicc_bfe_attach),
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DEVMETHOD(device_detach, quicc_bfe_detach),
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DEVMETHOD(bus_alloc_resource, quicc_bus_alloc_resource),
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DEVMETHOD(bus_release_resource, quicc_bus_release_resource),
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DEVMETHOD(bus_get_resource, quicc_bus_get_resource),
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DEVMETHOD(bus_read_ivar, quicc_bus_read_ivar),
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DEVMETHOD(bus_setup_intr, quicc_bus_setup_intr),
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DEVMETHOD(bus_teardown_intr, quicc_bus_teardown_intr),
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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{ 0, 0 }
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};
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static driver_t quicc_ocp_driver = {
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quicc_driver_name,
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quicc_ocp_methods,
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sizeof(struct quicc_softc),
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};
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static int
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quicc_ocp_probe(device_t dev)
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{
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device_t parent;
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uintptr_t clock, devtype;
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int error;
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parent = device_get_parent(dev);
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error = BUS_READ_IVAR(parent, dev, OCPBUS_IVAR_DEVTYPE, &devtype);
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if (error)
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return (error);
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if (devtype != OCPBUS_DEVTYPE_QUICC)
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return (ENXIO);
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if (BUS_READ_IVAR(parent, dev, OCPBUS_IVAR_CLOCK, &clock))
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clock = 0;
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return (quicc_bfe_probe(dev, clock));
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}
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DRIVER_MODULE(quicc, ocpbus, quicc_ocp_driver, quicc_devclass, 0, 0);
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