510ccb2fd4
to the actual handler routine. All the pointers are static-intialized to the only handlers available, and yet various platform-specific inits still set those pointers (to the values they're already initialized to). Begin to drain the swamp by removing all the redundant external declarations and runtime setting of the pointers that's scattered around various places.
693 lines
20 KiB
C
693 lines
20 KiB
C
/*-
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* machdep.c
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*
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* Machine dependant functions for kernel setup
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*
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* This file needs a lot of work.
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*
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* Created : 17/09/94
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sysproto.h>
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#include <sys/signalvar.h>
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#include <sys/imgact.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/linker.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/ptrace.h>
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#include <sys/cons.h>
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#include <sys/bio.h>
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#include <sys/bus.h>
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#include <sys/buf.h>
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#include <sys/exec.h>
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#include <sys/kdb.h>
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#include <sys/msgbuf.h>
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#include <machine/physmem.h>
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#include <machine/reg.h>
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#include <machine/cpu.h>
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#include <machine/board.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_object.h>
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#include <vm/vm_page.h>
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#include <vm/vm_map.h>
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#include <machine/devmap.h>
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#include <machine/vmparam.h>
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#include <machine/pcb.h>
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#include <machine/undefined.h>
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#include <machine/machdep.h>
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#include <machine/metadata.h>
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#include <machine/armreg.h>
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#include <machine/bus.h>
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#include <sys/reboot.h>
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#include <arm/at91/at91board.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91soc.h>
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#include <arm/at91/at91_usartreg.h>
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/at91sam9g20reg.h>
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#include <arm/at91/at91sam9g45reg.h>
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#ifndef MAXCPU
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#define MAXCPU 1
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#endif
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/* Page table for mapping proc0 zero page */
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#define KERNEL_PT_SYS 0
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#define KERNEL_PT_KERN 1
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#define KERNEL_PT_KERN_NUM 22
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/* L2 table for mapping after kernel */
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#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM
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#define KERNEL_PT_AFKERNEL_NUM 5
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/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
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#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
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struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
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/* Static device mappings. */
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const struct arm_devmap_entry at91_devmap[] = {
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/*
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* Map the critical on-board devices. The interrupt vector at
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* 0xffff0000 makes it impossible to map them PA == VA, so we map all
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* 0xfffxxxxx addresses to 0xdffxxxxx. This covers all critical devices
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* on all members of the AT91SAM9 and AT91RM9200 families.
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*/
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{
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0xdff00000,
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0xfff00000,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/* There's a notion that we should do the rest of these lazily. */
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/*
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* We can't just map the OHCI registers VA == PA, because
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* AT91xx_xxx_BASE belongs to the userland address space.
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* We could just choose a different virtual address, but a better
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* solution would probably be to just use pmap_mapdev() to allocate
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* KVA, as we don't need the OHCI controller before the vm
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* initialization is done. However, the AT91 resource allocation
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* system doesn't know how to use pmap_mapdev() yet.
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* Care must be taken to ensure PA and VM address do not overlap
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* between entries.
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*/
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{
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/*
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* Add the ohci controller, and anything else that might be
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* on this chip select for a VA/PA mapping.
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*/
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/* Internal Memory 1MB */
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AT91RM92_OHCI_VA_BASE,
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AT91RM92_OHCI_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{
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/* CompactFlash controller. Portion of EBI CS4 1MB */
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AT91RM92_CF_VA_BASE,
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AT91RM92_CF_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/*
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* The next two should be good for the 9260, 9261 and 9G20 since
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* addresses mapping is the same.
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*/
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{
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/* Internal Memory 1MB */
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AT91SAM9G20_OHCI_VA_BASE,
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AT91SAM9G20_OHCI_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{
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/* EBI CS3 256MB */
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AT91SAM9G20_NAND_VA_BASE,
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AT91SAM9G20_NAND_BASE,
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AT91SAM9G20_NAND_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/*
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* The next should be good for the 9G45.
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*/
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{
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/* Internal Memory 1MB */
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AT91SAM9G45_OHCI_VA_BASE,
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AT91SAM9G45_OHCI_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{ 0, 0, 0, 0, 0, }
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};
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/* Physical and virtual addresses for some global pages */
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struct pv_addr systempage;
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struct pv_addr msgbufpv;
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struct pv_addr irqstack;
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struct pv_addr undstack;
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struct pv_addr abtstack;
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struct pv_addr kernelstack;
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#ifdef LINUX_BOOT_ABI
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extern int membanks;
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extern int memstart[];
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extern int memsize[];
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#endif
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long
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at91_ramsize(void)
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{
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uint32_t cr, mdr, mr, *SDRAMC;
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int banks, rows, cols, bw;
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#ifdef LINUX_BOOT_ABI
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/*
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* If we found any ATAGs that were for memory, return the first bank.
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*/
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if (membanks > 0)
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return (memsize[0]);
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#endif
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if (at91_is_rm92()) {
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SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
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cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
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mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
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banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
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rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
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cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
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bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
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} else if (at91_cpu_is(AT91_T_SAM9G45)) {
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SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G45_DDRSDRC0_BASE);
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cr = SDRAMC[AT91SAM9G45_DDRSDRC_CR / 4];
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mdr = SDRAMC[AT91SAM9G45_DDRSDRC_MDR / 4];
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banks = 0;
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rows = ((cr & AT91SAM9G45_DDRSDRC_CR_NR_MASK) >> 2) + 11;
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cols = (cr & AT91SAM9G45_DDRSDRC_CR_NC_MASK) + 8;
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bw = (mdr & AT91SAM9G45_DDRSDRC_MDR_DBW_16) ? 1 : 2;
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/* Fix the calculation for DDR memory */
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mdr &= AT91SAM9G45_DDRSDRC_MDR_MASK;
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if (mdr & AT91SAM9G45_DDRSDRC_MDR_LPDDR1 ||
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mdr & AT91SAM9G45_DDRSDRC_MDR_DDR2) {
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/* The cols value is 1 higher for DDR */
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cols += 1;
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/* DDR has 4 internal banks. */
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banks = 2;
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}
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} else {
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/*
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* This should be good for the 9260, 9261, 9G20, 9G35 and 9X25
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* as addresses and registers are the same.
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*/
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SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
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cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
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mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];
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banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1;
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rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11;
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cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8;
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bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2;
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}
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return (1 << (cols + rows + banks + bw));
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}
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static const char *soc_type_name[] = {
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[AT91_T_CAP9] = "at91cap9",
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[AT91_T_RM9200] = "at91rm9200",
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[AT91_T_SAM9260] = "at91sam9260",
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[AT91_T_SAM9261] = "at91sam9261",
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[AT91_T_SAM9263] = "at91sam9263",
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[AT91_T_SAM9G10] = "at91sam9g10",
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[AT91_T_SAM9G20] = "at91sam9g20",
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[AT91_T_SAM9G45] = "at91sam9g45",
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[AT91_T_SAM9N12] = "at91sam9n12",
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[AT91_T_SAM9RL] = "at91sam9rl",
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[AT91_T_SAM9X5] = "at91sam9x5",
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[AT91_T_NONE] = "UNKNOWN"
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};
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static const char *soc_subtype_name[] = {
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[AT91_ST_NONE] = "UNKNOWN",
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[AT91_ST_RM9200_BGA] = "at91rm9200_bga",
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[AT91_ST_RM9200_PQFP] = "at91rm9200_pqfp",
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[AT91_ST_SAM9XE] = "at91sam9xe",
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[AT91_ST_SAM9G45] = "at91sam9g45",
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[AT91_ST_SAM9M10] = "at91sam9m10",
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[AT91_ST_SAM9G46] = "at91sam9g46",
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[AT91_ST_SAM9M11] = "at91sam9m11",
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[AT91_ST_SAM9G15] = "at91sam9g15",
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[AT91_ST_SAM9G25] = "at91sam9g25",
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[AT91_ST_SAM9G35] = "at91sam9g35",
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[AT91_ST_SAM9X25] = "at91sam9x25",
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[AT91_ST_SAM9X35] = "at91sam9x35",
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};
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struct at91_soc_info soc_info;
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/*
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* Read the SoC ID from the CIDR register and try to match it against the
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* values we know. If we find a good one, we return true. If not, we
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* return false. When we find a good one, we also find the subtype
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* and CPU family.
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*/
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static int
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at91_try_id(uint32_t dbgu_base)
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{
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uint32_t socid;
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soc_info.cidr = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
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DBGU_C1R);
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socid = soc_info.cidr & ~AT91_CPU_VERSION_MASK;
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soc_info.type = AT91_T_NONE;
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soc_info.subtype = AT91_ST_NONE;
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soc_info.family = (soc_info.cidr & AT91_CPU_FAMILY_MASK) >> 20;
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soc_info.exid = *(volatile uint32_t *)(AT91_BASE + dbgu_base +
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DBGU_C2R);
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switch (socid) {
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case AT91_CPU_CAP9:
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soc_info.type = AT91_T_CAP9;
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break;
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case AT91_CPU_RM9200:
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soc_info.type = AT91_T_RM9200;
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break;
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case AT91_CPU_SAM9XE128:
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case AT91_CPU_SAM9XE256:
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case AT91_CPU_SAM9XE512:
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case AT91_CPU_SAM9260:
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soc_info.type = AT91_T_SAM9260;
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if (soc_info.family == AT91_FAMILY_SAM9XE)
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soc_info.subtype = AT91_ST_SAM9XE;
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break;
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case AT91_CPU_SAM9261:
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soc_info.type = AT91_T_SAM9261;
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break;
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case AT91_CPU_SAM9263:
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soc_info.type = AT91_T_SAM9263;
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break;
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case AT91_CPU_SAM9G10:
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soc_info.type = AT91_T_SAM9G10;
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break;
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case AT91_CPU_SAM9G20:
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soc_info.type = AT91_T_SAM9G20;
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break;
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case AT91_CPU_SAM9G45:
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soc_info.type = AT91_T_SAM9G45;
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break;
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case AT91_CPU_SAM9N12:
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soc_info.type = AT91_T_SAM9N12;
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break;
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case AT91_CPU_SAM9RL64:
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soc_info.type = AT91_T_SAM9RL;
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break;
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case AT91_CPU_SAM9X5:
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soc_info.type = AT91_T_SAM9X5;
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break;
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default:
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return (0);
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}
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switch (soc_info.type) {
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case AT91_T_SAM9G45:
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switch (soc_info.exid) {
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case AT91_EXID_SAM9G45:
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soc_info.subtype = AT91_ST_SAM9G45;
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break;
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case AT91_EXID_SAM9G46:
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soc_info.subtype = AT91_ST_SAM9G46;
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break;
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case AT91_EXID_SAM9M10:
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soc_info.subtype = AT91_ST_SAM9M10;
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break;
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case AT91_EXID_SAM9M11:
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soc_info.subtype = AT91_ST_SAM9M11;
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break;
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}
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break;
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case AT91_T_SAM9X5:
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switch (soc_info.exid) {
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case AT91_EXID_SAM9G15:
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soc_info.subtype = AT91_ST_SAM9G15;
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break;
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case AT91_EXID_SAM9G25:
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soc_info.subtype = AT91_ST_SAM9G25;
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break;
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case AT91_EXID_SAM9G35:
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soc_info.subtype = AT91_ST_SAM9G35;
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break;
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case AT91_EXID_SAM9X25:
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soc_info.subtype = AT91_ST_SAM9X25;
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break;
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case AT91_EXID_SAM9X35:
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soc_info.subtype = AT91_ST_SAM9X35;
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break;
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}
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break;
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default:
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break;
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}
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/*
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* Disable interrupts in the DBGU unit...
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*/
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*(volatile uint32_t *)(AT91_BASE + dbgu_base + USART_IDR) = 0xffffffff;
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/*
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* Save the name for later...
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*/
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snprintf(soc_info.name, sizeof(soc_info.name), "%s%s%s",
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soc_type_name[soc_info.type],
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soc_info.subtype == AT91_ST_NONE ? "" : " subtype ",
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soc_info.subtype == AT91_ST_NONE ? "" :
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soc_subtype_name[soc_info.subtype]);
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/*
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* try to get the matching CPU support.
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*/
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soc_info.soc_data = at91_match_soc(soc_info.type, soc_info.subtype);
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soc_info.dbgu_base = AT91_BASE + dbgu_base;
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return (1);
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}
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void
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at91_soc_id(void)
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{
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if (!at91_try_id(AT91_DBGU0))
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at91_try_id(AT91_DBGU1);
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}
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#ifdef ARM_MANY_BOARD
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/* likely belongs in arm/arm/machdep.c, but since board_init is still at91 only... */
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SET_DECLARE(arm_board_set, const struct arm_board);
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|
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/* Not yet fully functional, but enough to build ATMEL config */
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static long
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board_init(void)
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{
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return -1;
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}
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#endif
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void *
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initarm(struct arm_boot_params *abp)
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{
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struct pv_addr kernel_l1pt;
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struct pv_addr dpcpu;
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int i;
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u_int l1pagetable;
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vm_offset_t freemempos;
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vm_offset_t afterkern;
|
|
uint32_t memsize;
|
|
vm_offset_t lastaddr;
|
|
|
|
lastaddr = parse_boot_param(abp);
|
|
arm_physmem_kernaddr = abp->abp_physaddr;
|
|
set_cpufuncs();
|
|
pcpu0_init();
|
|
|
|
/* Do basic tuning, hz etc */
|
|
init_param1();
|
|
|
|
freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
|
|
/* Define a macro to simplify memory allocation */
|
|
#define valloc_pages(var, np) \
|
|
alloc_pages((var).pv_va, (np)); \
|
|
(var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR);
|
|
|
|
#define alloc_pages(var, np) \
|
|
(var) = freemempos; \
|
|
freemempos += (np * PAGE_SIZE); \
|
|
memset((char *)(var), 0, ((np) * PAGE_SIZE));
|
|
|
|
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
|
|
freemempos += PAGE_SIZE;
|
|
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
|
|
for (i = 0; i < NUM_KERNEL_PTS; ++i) {
|
|
if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
|
|
valloc_pages(kernel_pt_table[i],
|
|
L2_TABLE_SIZE / PAGE_SIZE);
|
|
} else {
|
|
kernel_pt_table[i].pv_va = freemempos -
|
|
(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
|
|
L2_TABLE_SIZE_REAL;
|
|
kernel_pt_table[i].pv_pa =
|
|
kernel_pt_table[i].pv_va - KERNVIRTADDR +
|
|
abp->abp_physaddr;
|
|
}
|
|
}
|
|
/*
|
|
* Allocate a page for the system page mapped to 0x00000000
|
|
* or 0xffff0000. This page will just contain the system vectors
|
|
* and can be shared by all processes.
|
|
*/
|
|
valloc_pages(systempage, 1);
|
|
|
|
/* Allocate dynamic per-cpu area. */
|
|
valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
|
|
dpcpu_init((void *)dpcpu.pv_va, 0);
|
|
|
|
/* Allocate stacks for all modes */
|
|
valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU);
|
|
valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU);
|
|
valloc_pages(undstack, UND_STACK_SIZE * MAXCPU);
|
|
valloc_pages(kernelstack, KSTACK_PAGES * MAXCPU);
|
|
valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
|
|
|
|
/*
|
|
* Now we start construction of the L1 page table
|
|
* We start by mapping the L2 page tables into the L1.
|
|
* This means that we can replace L1 mappings later on if necessary
|
|
*/
|
|
l1pagetable = kernel_l1pt.pv_va;
|
|
|
|
/* Map the L2 pages tables in the L1 page table */
|
|
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
|
|
&kernel_pt_table[KERNEL_PT_SYS]);
|
|
for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
|
|
pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE,
|
|
&kernel_pt_table[KERNEL_PT_KERN + i]);
|
|
pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
|
|
(((uint32_t)lastaddr - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
|
|
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
|
|
afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - 1));
|
|
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
|
|
pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE,
|
|
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
|
|
}
|
|
|
|
/* Map the vector page. */
|
|
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
|
|
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
|
|
|
|
/* Map the DPCPU pages */
|
|
pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE,
|
|
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
|
|
|
|
/* Map the stack pages */
|
|
pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
|
|
IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
|
|
pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
|
|
ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
|
|
pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
|
|
UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
|
|
pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
|
|
KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
|
|
|
|
pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
|
|
L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
|
|
pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
|
|
msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
|
|
|
|
for (i = 0; i < NUM_KERNEL_PTS; ++i) {
|
|
pmap_map_chunk(l1pagetable, kernel_pt_table[i].pv_va,
|
|
kernel_pt_table[i].pv_pa, L2_TABLE_SIZE,
|
|
VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
|
|
}
|
|
|
|
arm_devmap_bootstrap(l1pagetable, at91_devmap);
|
|
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT);
|
|
setttb(kernel_l1pt.pv_pa);
|
|
cpu_tlb_flushID();
|
|
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2));
|
|
|
|
at91_soc_id();
|
|
|
|
/*
|
|
* Initialize all the clocks, so that the console can work. We can only
|
|
* do this if at91_soc_id() was able to fill in the support data. Even
|
|
* if we can't init the clocks, still try to do a console init so we can
|
|
* try to print the error message about missing soc support. There's a
|
|
* chance the printf will work if the bootloader set up the DBGU.
|
|
*/
|
|
if (soc_info.soc_data != NULL) {
|
|
soc_info.soc_data->soc_clock_init();
|
|
at91_pmc_init_clock();
|
|
}
|
|
|
|
cninit();
|
|
|
|
if (soc_info.soc_data == NULL)
|
|
printf("Warning: No soc support for %s found.\n", soc_info.name);
|
|
|
|
memsize = board_init();
|
|
if (memsize == -1) {
|
|
printf("board_init() failed, cannot determine ram size; "
|
|
"assuming 16MB\n");
|
|
memsize = 16 * 1024 * 1024;
|
|
}
|
|
|
|
/*
|
|
* Pages were allocated during the secondary bootstrap for the
|
|
* stacks for different CPU modes.
|
|
* We must now set the r13 registers in the different CPU modes to
|
|
* point to these stacks.
|
|
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
|
|
* of the stack memory.
|
|
*/
|
|
cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
|
|
cpu_setup("");
|
|
|
|
set_stackptrs(0);
|
|
|
|
/*
|
|
* We must now clean the cache again....
|
|
* Cleaning may be done by reading new data to displace any
|
|
* dirty data in the cache. This will have happened in setttb()
|
|
* but since we are boot strapping the addresses used for the read
|
|
* may have just been remapped and thus the cache could be out
|
|
* of sync. A re-clean after the switch will cure this.
|
|
* After booting there are no gross relocations of the kernel thus
|
|
* this problem will not occur after initarm().
|
|
*/
|
|
cpu_idcache_wbinv_all();
|
|
|
|
undefined_init();
|
|
|
|
init_proc0(kernelstack.pv_va);
|
|
|
|
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
|
|
|
|
pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1);
|
|
/* Always use the 256MB of KVA we have available between the kernel and devices */
|
|
vm_max_kernel_address = KERNVIRTADDR + (256 << 20);
|
|
pmap_bootstrap(freemempos, &kernel_l1pt);
|
|
msgbufp = (void*)msgbufpv.pv_va;
|
|
msgbufinit(msgbufp, msgbufsize);
|
|
mutex_init();
|
|
|
|
/*
|
|
* Add the physical ram we have available.
|
|
*
|
|
* Exclude the kernel, and all the things we allocated which immediately
|
|
* follow the kernel, from the VM allocation pool but not from crash
|
|
* dumps. virtual_avail is a global variable which tracks the kva we've
|
|
* "allocated" while setting up pmaps.
|
|
*
|
|
* Prepare the list of physical memory available to the vm subsystem.
|
|
*/
|
|
arm_physmem_hardware_region(PHYSADDR, memsize);
|
|
arm_physmem_exclude_region(abp->abp_physaddr,
|
|
virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
|
|
arm_physmem_init_kernel_globals();
|
|
|
|
init_param2(physmem);
|
|
kdb_init();
|
|
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
|
|
sizeof(struct pcb)));
|
|
}
|
|
|
|
/*
|
|
* These functions are handled elsewhere, so make them nops here.
|
|
*/
|
|
void
|
|
cpu_startprofclock(void)
|
|
{
|
|
|
|
}
|
|
|
|
void
|
|
cpu_stopprofclock(void)
|
|
{
|
|
|
|
}
|
|
|
|
void
|
|
cpu_initclocks(void)
|
|
{
|
|
|
|
}
|
|
|
|
void
|
|
DELAY(int n)
|
|
{
|
|
|
|
if (soc_info.soc_data)
|
|
soc_info.soc_data->soc_delay(n);
|
|
}
|
|
|
|
void
|
|
cpu_reset(void)
|
|
{
|
|
|
|
if (soc_info.soc_data)
|
|
soc_info.soc_data->soc_reset();
|
|
while (1)
|
|
continue;
|
|
}
|