Justin Hibbits 6640579610 msun fixes for SPE ... Summary: Fix FPU exception management for powerpcspe. Bits are in a different place from the standard FPSCR, so we need to handle the shifting differences. Also, there's no concept of a "software exception" raise, so we need to do exceptional math to trigger the exception from software. Reviewed By: alfredo Differential Revision: https://reviews.freebsd.org/D22824		2021-05-05 20:57:33 -05:00
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aarch64	Save all fpcr/fpsr bits in the AArch64 fenv_t	2021-03-12 17:01:41 +00:00
amd64	libm: Add missing END() directives for amd64 routines	2019-10-23 16:05:52 +00:00
arm
bsdsrc	msun: drop clause 3 from the Berkeley license.	2019-12-27 01:11:26 +00:00
i387	Add CFI start/end proc directives to arm64, i386, and ppc	2020-12-05 00:33:28 +00:00
ld80	lib/msun: Fix x86 GCC6 build after 221622ec0c	2021-03-12 18:44:44 +00:00
ld128	lib/msun: Avoid FE_INEXACT for x86 log2l/log10l	2021-03-08 09:39:32 +00:00
man	Fix a few mandoc issues	2020-10-09 19:12:44 +00:00
mips
powerpc	msun fixes for SPE	2021-05-05 20:57:33 -05:00
riscv	RISC-V: Fix feenableexcept return value	2021-03-25 11:16:20 +00:00
src	Avoid -pedantic warnings about using _Generic in __fp_type_select	2021-04-08 18:20:32 +02:00
tests	Allow lib/msun/logarithm_test to pass on ld128 platforms	2021-04-20 01:46:43 +01:00
x86	Resolve conflicts between macros in fenv.h and ieeefp.h	2018-05-31 20:22:47 +00:00
Makefile	lib/msun: Exclude ignored-pragmas from -Werror	2021-04-15 16:27:52 +01:00
Makefile.depend	Update Makefile.depend files	2019-12-11 17:37:53 +00:00
Symbol.map	msun: add ld80/ld128 powl, cpow, cpowf, cpowl from openbsd	2018-07-15 00:23:10 +00:00