212 lines
8.5 KiB
C
212 lines
8.5 KiB
C
/* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership.
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* The ASF licenses this file to You under the Apache License, Version 2.0
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* (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "apr_arch_atomic.h"
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#ifdef USE_ATOMICS_PPC
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#ifdef PPC405_ERRATA
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# define PPC405_ERR77_SYNC " sync\n"
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#else
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# define PPC405_ERR77_SYNC
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#endif
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APR_DECLARE(apr_status_t) apr_atomic_init(apr_pool_t *p)
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{
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#if defined (NEED_ATOMICS_GENERIC64)
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return apr__atomic_generic64_init(p);
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#else
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return APR_SUCCESS;
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#endif
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}
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APR_DECLARE(apr_uint32_t) apr_atomic_read32(volatile apr_uint32_t *mem)
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{
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return *mem;
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}
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APR_DECLARE(void) apr_atomic_set32(volatile apr_uint32_t *mem, apr_uint32_t val)
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{
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*mem = val;
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}
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APR_DECLARE(apr_uint32_t) apr_atomic_add32(volatile apr_uint32_t *mem, apr_uint32_t val)
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{
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apr_uint32_t prev, temp;
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asm volatile ("1:\n" /* lost reservation */
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" lwarx %0,0,%3\n" /* load and reserve */
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" add %1,%0,%4\n" /* add val and prev */
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PPC405_ERR77_SYNC /* ppc405 Erratum 77 */
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" stwcx. %1,0,%3\n" /* store new value */
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" bne- 1b\n" /* loop if lost */
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: "=&r" (prev), "=&r" (temp), "=m" (*mem)
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: "b" (mem), "r" (val)
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: "cc", "memory");
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return prev;
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}
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APR_DECLARE(void) apr_atomic_sub32(volatile apr_uint32_t *mem, apr_uint32_t val)
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{
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apr_uint32_t temp;
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asm volatile ("1:\n" /* lost reservation */
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" lwarx %0,0,%2\n" /* load and reserve */
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" subf %0,%3,%0\n" /* subtract val */
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PPC405_ERR77_SYNC /* ppc405 Erratum 77 */
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" stwcx. %0,0,%2\n" /* store new value */
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" bne- 1b\n" /* loop if lost */
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: "=&r" (temp), "=m" (*mem)
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: "b" (mem), "r" (val)
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: "cc", "memory");
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}
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APR_DECLARE(apr_uint32_t) apr_atomic_inc32(volatile apr_uint32_t *mem)
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{
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apr_uint32_t prev;
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asm volatile ("1:\n" /* lost reservation */
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" lwarx %0,0,%2\n" /* load and reserve */
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" addi %0,%0,1\n" /* add immediate */
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PPC405_ERR77_SYNC /* ppc405 Erratum 77 */
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" stwcx. %0,0,%2\n" /* store new value */
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" bne- 1b\n" /* loop if lost */
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" subi %0,%0,1\n" /* return old value */
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: "=&b" (prev), "=m" (*mem)
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: "b" (mem), "m" (*mem)
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: "cc", "memory");
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return prev;
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}
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APR_DECLARE(int) apr_atomic_dec32(volatile apr_uint32_t *mem)
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{
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apr_uint32_t prev;
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asm volatile ("1:\n" /* lost reservation */
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" lwarx %0,0,%2\n" /* load and reserve */
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" subi %0,%0,1\n" /* subtract immediate */
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PPC405_ERR77_SYNC /* ppc405 Erratum 77 */
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" stwcx. %0,0,%2\n" /* store new value */
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" bne- 1b\n" /* loop if lost */
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: "=&b" (prev), "=m" (*mem)
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: "b" (mem), "m" (*mem)
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: "cc", "memory");
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return prev;
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}
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APR_DECLARE(apr_uint32_t) apr_atomic_cas32(volatile apr_uint32_t *mem, apr_uint32_t with,
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apr_uint32_t cmp)
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{
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apr_uint32_t prev;
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asm volatile ("1:\n" /* lost reservation */
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" lwarx %0,0,%1\n" /* load and reserve */
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" cmpw %0,%3\n" /* compare operands */
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" bne- exit_%=\n" /* skip if not equal */
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PPC405_ERR77_SYNC /* ppc405 Erratum 77 */
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" stwcx. %2,0,%1\n" /* store new value */
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" bne- 1b\n" /* loop if lost */
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"exit_%=:\n" /* not equal */
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: "=&r" (prev)
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: "b" (mem), "r" (with), "r" (cmp)
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: "cc", "memory");
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return prev;
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}
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APR_DECLARE(apr_uint32_t) apr_atomic_xchg32(volatile apr_uint32_t *mem, apr_uint32_t val)
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{
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apr_uint32_t prev;
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asm volatile ("1:\n" /* lost reservation */
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" lwarx %0,0,%1\n" /* load and reserve */
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PPC405_ERR77_SYNC /* ppc405 Erratum 77 */
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" stwcx. %2,0,%1\n" /* store new value */
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" bne- 1b" /* loop if lost */
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: "=&r" (prev)
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: "b" (mem), "r" (val)
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: "cc", "memory");
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return prev;
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}
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APR_DECLARE(void*) apr_atomic_casptr(volatile void **mem, void *with, const void *cmp)
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{
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void *prev;
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#if APR_SIZEOF_VOIDP == 4
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asm volatile ("1:\n" /* lost reservation */
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" lwarx %0,0,%1\n" /* load and reserve */
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" cmpw %0,%3\n" /* compare operands */
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" bne- 2f\n" /* skip if not equal */
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PPC405_ERR77_SYNC /* ppc405 Erratum 77 */
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" stwcx. %2,0,%1\n" /* store new value */
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" bne- 1b\n" /* loop if lost */
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"2:\n" /* not equal */
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: "=&r" (prev)
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: "b" (mem), "r" (with), "r" (cmp)
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: "cc", "memory");
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#elif APR_SIZEOF_VOIDP == 8
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asm volatile ("1:\n" /* lost reservation */
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" ldarx %0,0,%1\n" /* load and reserve */
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" cmpd %0,%3\n" /* compare operands */
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" bne- 2f\n" /* skip if not equal */
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PPC405_ERR77_SYNC /* ppc405 Erratum 77 */
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" stdcx. %2,0,%1\n" /* store new value */
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" bne- 1b\n" /* loop if lost */
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"2:\n" /* not equal */
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: "=&r" (prev)
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: "b" (mem), "r" (with), "r" (cmp)
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: "cc", "memory");
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#else
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#error APR_SIZEOF_VOIDP value not supported
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#endif
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return prev;
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}
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APR_DECLARE(void*) apr_atomic_xchgptr(volatile void **mem, void *with)
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{
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void *prev;
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#if APR_SIZEOF_VOIDP == 4
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asm volatile ("1:\n" /* lost reservation */
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" lwarx %0,0,%1\n" /* load and reserve */
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PPC405_ERR77_SYNC /* ppc405 Erratum 77 */
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" stwcx. %2,0,%1\n" /* store new value */
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" bne- 1b\n" /* loop if lost */
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" isync\n" /* memory barrier */
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: "=&r" (prev)
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: "b" (mem), "r" (with)
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: "cc", "memory");
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#elif APR_SIZEOF_VOIDP == 8
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asm volatile ("1:\n" /* lost reservation */
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" ldarx %0,0,%1\n" /* load and reserve */
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PPC405_ERR77_SYNC /* ppc405 Erratum 77 */
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" stdcx. %2,0,%1\n" /* store new value */
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" bne- 1b\n" /* loop if lost */
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" isync\n" /* memory barrier */
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: "=&r" (prev)
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: "b" (mem), "r" (with)
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: "cc", "memory");
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#else
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#error APR_SIZEOF_VOIDP value not supported
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#endif
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return prev;
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}
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#endif /* USE_ATOMICS_PPC */
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