4948f4b8d5
Executive is a library that can be used by standalone applications and kernels to abstract access to Octeon SoC and board-specific hardware and facilities. The FreeBSD port to Octeon will be updated to use this where possible.
365 lines
12 KiB
C
365 lines
12 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to the Level 2 Cache (L2C) control, measurement, and debugging
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* facilities.
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*
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* <hr>$Revision: 41586 $<hr>
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*
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*/
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#ifndef __CVMX_L2C_H__
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#define __CVMX_L2C_H__
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#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */
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#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */
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#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */
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#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */
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#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
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/* Defines for index aliasing computations */
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#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
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#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
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/*------------*/
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/* TYPEDEFS */
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/*------------*/
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typedef union { // L2C Tag/Data Store Debug Register
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uint64_t u64;
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struct {
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uint64_t reserved: 32,
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lfb_enum: 4,
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lfb_dmp: 1,
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ppnum: 4,
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set: 3,
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finv: 1,
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l2d: 1,
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l2t: 1;
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};
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} cvmx_l2c_dbg;
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typedef union
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{
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uint64_t u64;
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#if __BYTE_ORDER == __BIG_ENDIAN
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struct
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{
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uint64_t reserved : 28;
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uint64_t V : 1; // Line valid
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uint64_t D : 1; // Line dirty
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uint64_t L : 1; // Line locked
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uint64_t U : 1; // Use, LRU eviction
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uint64_t addr : 32; // Phys mem (not all bits valid)
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} s;
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#endif
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} cvmx_l2c_tag_t;
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/* L2C Performance Counter events. */
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typedef enum
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{
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CVMX_L2C_EVENT_CYCLES = 0,
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CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
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CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
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CVMX_L2C_EVENT_DATA_MISS = 3,
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CVMX_L2C_EVENT_DATA_HIT = 4,
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CVMX_L2C_EVENT_MISS = 5,
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CVMX_L2C_EVENT_HIT = 6,
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CVMX_L2C_EVENT_VICTIM_HIT = 7,
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CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
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CVMX_L2C_EVENT_TAG_PROBE = 9,
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CVMX_L2C_EVENT_TAG_UPDATE = 10,
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CVMX_L2C_EVENT_TAG_COMPLETE = 11,
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CVMX_L2C_EVENT_TAG_DIRTY = 12,
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CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
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CVMX_L2C_EVENT_DATA_STORE_READ = 14,
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CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
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CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
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CVMX_L2C_EVENT_WRITE_REQUEST = 17,
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CVMX_L2C_EVENT_READ_REQUEST = 18,
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CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
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CVMX_L2C_EVENT_XMC_NOP = 20,
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CVMX_L2C_EVENT_XMC_LDT = 21,
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CVMX_L2C_EVENT_XMC_LDI = 22,
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CVMX_L2C_EVENT_XMC_LDD = 23,
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CVMX_L2C_EVENT_XMC_STF = 24,
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CVMX_L2C_EVENT_XMC_STT = 25,
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CVMX_L2C_EVENT_XMC_STP = 26,
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CVMX_L2C_EVENT_XMC_STC = 27,
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CVMX_L2C_EVENT_XMC_DWB = 28,
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CVMX_L2C_EVENT_XMC_PL2 = 29,
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CVMX_L2C_EVENT_XMC_PSL1 = 30,
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CVMX_L2C_EVENT_XMC_IOBLD = 31,
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CVMX_L2C_EVENT_XMC_IOBST = 32,
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CVMX_L2C_EVENT_XMC_IOBDMA = 33,
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CVMX_L2C_EVENT_XMC_IOBRSP = 34,
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CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
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CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
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CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
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CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
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CVMX_L2C_EVENT_RSC_NOP = 39,
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CVMX_L2C_EVENT_RSC_STDN = 40,
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CVMX_L2C_EVENT_RSC_FILL = 41,
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CVMX_L2C_EVENT_RSC_REFL = 42,
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CVMX_L2C_EVENT_RSC_STIN = 43,
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CVMX_L2C_EVENT_RSC_SCIN = 44,
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CVMX_L2C_EVENT_RSC_SCFL = 45,
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CVMX_L2C_EVENT_RSC_SCDN = 46,
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CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
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CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
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CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
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CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
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CVMX_L2C_EVENT_LRF_REQ = 51,
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CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
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CVMX_L2C_EVENT_DT_WR_INVAL = 53
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} cvmx_l2c_event_t;
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/**
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* Configure one of the four L2 Cache performance counters to capture event
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* occurences.
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*
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* @param counter The counter to configure. Range 0..3.
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* @param event The type of L2 Cache event occurrence to count.
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* @param clear_on_read When asserted, any read of the performance counter
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* clears the counter.
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*
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* @note The routine does not clear the counter.
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*/
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void cvmx_l2c_config_perf(uint32_t counter,
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cvmx_l2c_event_t event,
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uint32_t clear_on_read);
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/**
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* Read the given L2 Cache performance counter. The counter must be configured
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* before reading, but this routine does not enforce this requirement.
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*
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* @param counter The counter to configure. Range 0..3.
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*
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* @return The current counter value.
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*/
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uint64_t cvmx_l2c_read_perf(uint32_t counter);
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/**
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* Return the L2 Cache way partitioning for a given core.
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*
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* @param core The core processor of interest.
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*
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* @return The mask specifying the partitioning. 0 bits in mask indicates
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* the cache 'ways' that a core can evict from.
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* -1 on error
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*/
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int cvmx_l2c_get_core_way_partition(uint32_t core);
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/**
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* Partitions the L2 cache for a core
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*
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* @param core The core that the partitioning applies to.
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* @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
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* to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines
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* from that way. There must be at least one allowed way (0 bit) in the mask.
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*
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* @note If any ways are blocked for all cores and the HW blocks, then those ways will never have
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* any cache lines evicted from them. All cores and the hardware blocks are free to read from
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* all ways regardless of the partitioning.
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*/
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int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
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/**
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* Return the L2 Cache way partitioning for the hw blocks.
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*
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* @return The mask specifying the reserved way. 0 bits in mask indicates
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* the cache 'ways' that a core can evict from.
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* -1 on error
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*/
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int cvmx_l2c_get_hw_way_partition(void);
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/**
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* Partitions the L2 cache for the hardware blocks.
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*
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* @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
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* to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines
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* from that way. There must be at least one allowed way (0 bit) in the mask.
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*
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* @note If any ways are blocked for all cores and the HW blocks, then those ways will never have
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* any cache lines evicted from them. All cores and the hardware blocks are free to read from
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* all ways regardless of the partitioning.
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*/
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int cvmx_l2c_set_hw_way_partition(uint32_t mask);
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/**
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* Locks a line in the L2 cache at the specified physical address
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*
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* @param addr physical address of line to lock
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*
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* @return 0 on success,
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* 1 if line not locked.
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*/
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int cvmx_l2c_lock_line(uint64_t addr);
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/**
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* Locks a specified memory region in the L2 cache.
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*
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* Note that if not all lines can be locked, that means that all
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* but one of the ways (associations) available to the locking
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* core are locked. Having only 1 association available for
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* normal caching may have a significant adverse affect on performance.
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* Care should be taken to ensure that enough of the L2 cache is left
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* unlocked to allow for normal caching of DRAM.
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*
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* @param start Physical address of the start of the region to lock
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* @param len Length (in bytes) of region to lock
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*
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* @return Number of requested lines that where not locked.
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* 0 on success (all locked)
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*/
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int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
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/**
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* Unlock and flush a cache line from the L2 cache.
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* IMPORTANT: Must only be run by one core at a time due to use
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* of L2C debug features.
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* Note that this function will flush a matching but unlocked cache line.
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* (If address is not in L2, no lines are flushed.)
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*
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* @param address Physical address to unlock
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*
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* @return 0: line not unlocked
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* 1: line unlocked
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*/
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int cvmx_l2c_unlock_line(uint64_t address);
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/**
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* Unlocks a region of memory that is locked in the L2 cache
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*
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* @param start start physical address
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* @param len length (in bytes) to unlock
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*
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* @return Number of locked lines that the call unlocked
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*/
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int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
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/**
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* Read the L2 controller tag for a given location in L2
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*
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* @param association
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* Which association to read line from
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* @param index Which way to read from.
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*
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* @return l2c tag structure for line requested.
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*/
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cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index);
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/* Wrapper around deprecated old function name */
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static inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association, uint32_t index)
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{
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return cvmx_l2c_get_tag(association, index);
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}
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/**
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* Returns the cache index for a given physical address
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*
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* @param addr physical address
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*
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* @return L2 cache index
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*/
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uint32_t cvmx_l2c_address_to_index (uint64_t addr);
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/**
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* Flushes (and unlocks) the entire L2 cache.
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* IMPORTANT: Must only be run by one core at a time due to use
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* of L2C debug features.
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*/
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void cvmx_l2c_flush(void);
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/**
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*
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* @return Returns the size of the L2 cache in bytes,
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* -1 on error (unrecognized model)
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*/
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int cvmx_l2c_get_cache_size_bytes(void);
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/**
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* Return the number of sets in the L2 Cache
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*
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* @return
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*/
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int cvmx_l2c_get_num_sets(void);
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/**
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* Return log base 2 of the number of sets in the L2 cache
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* @return
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*/
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int cvmx_l2c_get_set_bits(void);
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/**
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* Return the number of associations in the L2 Cache
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*
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* @return
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*/
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int cvmx_l2c_get_num_assoc(void);
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/**
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* Flush a line from the L2 cache
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* This should only be called from one core at a time, as this routine
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* sets the core to the 'debug' core in order to flush the line.
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*
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* @param assoc Association (or way) to flush
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* @param index Index to flush
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*/
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void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
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#endif /* __CVMX_L2C_H__ */
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