5f00d121ef
sound cards with optional pseudo-multichannel playback.
It's based on snd_emu10k1 sound driver. Single channel version is available
from audio/emu10kx port since some time.
The two new ALSA header files (GPLed), which contain Audigy 2 ("p16v") and
Audigy 2 Value ("p17v") specific interfaces, are latest versions from ALSA
Mercurial repository.
This is not connected to the build yet.
Submitted by: Yuriy Tsibizov <Yuriy.Tsibizov@gfk.ru>
302 lines
15 KiB
C
302 lines
15 KiB
C
/*-
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* Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
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* Driver p16v chips
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* Version: 0.21
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*
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* FEATURES currently supported:
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* Output fixed at S32_LE, 2 channel to hw:0,0
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* Rates: 44.1, 48, 96, 192.
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*
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* Changelog:
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* 0.8
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* Use separate card based buffer for periods table.
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* 0.9
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* Use 2 channel output streams instead of 8 channel.
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* (8 channel output streams might be good for ASIO type output)
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* Corrected speaker output, so Front -> Front etc.
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* 0.10
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* Fixed missed interrupts.
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* 0.11
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* Add Sound card model number and names.
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* Add Analog volume controls.
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* 0.12
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* Corrected playback interrupts. Now interrupt per period, instead of half period.
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* 0.13
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* Use single trigger for multichannel.
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* 0.14
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* Mic capture now works at fixed: S32_LE, 96000Hz, Stereo.
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* 0.15
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* Force buffer_size / period_size == INTEGER.
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* 0.16
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* Update p16v.c to work with changed alsa api.
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* 0.17
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* Update p16v.c to work with changed alsa api. Removed boot_devs.
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* 0.18
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* Merging with snd-emu10k1 driver.
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* 0.19
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* One stereo channel at 24bit now works.
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* 0.20
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* Added better register defines.
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* 0.21
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* Split from p16v.c
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*
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*
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* BUGS:
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* Some stability problems when unloading the snd-p16v kernel module.
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* --
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*
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* TODO:
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* SPDIF out.
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* Find out how to change capture sample rates. E.g. To record SPDIF at 48000Hz.
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* Currently capture fixed at 48000Hz.
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*
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* --
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* GENERAL INFO:
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* Model: SB0240
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* P16V Chip: CA0151-DBS
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* Audigy 2 Chip: CA0102-IAT
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* AC97 Codec: STAC 9721
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* ADC: Philips 1361T (Stereo 24bit)
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* DAC: CS4382-K (8-channel, 24bit, 192Khz)
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*
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* This code was initally based on code from ALSA's emu10k1x.c which is:
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* Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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/* $FreeBSD$ */
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/********************************************************************************************************/
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/* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers */
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/********************************************************************************************************/
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/* The sample rate of the SPDIF outputs is set by modifying a register in the EMU10K2 PTR register A_SPDIF_SAMPLERATE.
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* The sample rate is also controlled by the same registers that control the rate of the EMU10K2 sample rate converters.
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*/
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/* Initally all registers from 0x00 to 0x3f have zero contents. */
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#define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */
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/* One list entry: 4 bytes for DMA address,
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* 4 bytes for period_size << 16.
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* One list entry is 8 bytes long.
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* One list entry for each period in the buffer.
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*/
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#define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
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#define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */
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#define PLAYBACK_UNKNOWN3 0x03 /* Not used */
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#define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA addresss */
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#define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size. win2000 uses 0x04000000 */
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#define PLAYBACK_POINTER 0x06 /* Playback period pointer. Used with PLAYBACK_LIST_PTR to determine buffer position currently in DAC */
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#define PLAYBACK_FIFO_END_ADDRESS 0x07 /* Playback FIFO end address */
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#define PLAYBACK_FIFO_POINTER 0x08 /* Playback FIFO pointer and number of valid sound samples in cache */
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#define PLAYBACK_UNKNOWN9 0x09 /* Not used */
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#define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */
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#define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */
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#define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */
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#define CAPTURE_FIFO_POINTER 0x13 /* Capture FIFO pointer and number of valid sound samples in cache */
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#define CAPTURE_P16V_VOLUME1 0x14 /* Low: Capture volume 0xXXXX3030 */
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#define CAPTURE_P16V_VOLUME2 0x15 /* High:Has no effect on capture volume */
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#define CAPTURE_P16V_SOURCE 0x16 /* P16V source select. Set to 0x0700E4E5 for AC97 CAPTURE */
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/* [0:1] Capture input 0 channel select. 0 = Capture output 0.
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* 1 = Capture output 1.
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* 2 = Capture output 2.
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* 3 = Capture output 3.
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* [3:2] Capture input 1 channel select. 0 = Capture output 0.
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* 1 = Capture output 1.
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* 2 = Capture output 2.
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* 3 = Capture output 3.
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* [5:4] Capture input 2 channel select. 0 = Capture output 0.
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* 1 = Capture output 1.
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* 2 = Capture output 2.
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* 3 = Capture output 3.
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* [7:6] Capture input 3 channel select. 0 = Capture output 0.
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* 1 = Capture output 1.
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* 2 = Capture output 2.
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* 3 = Capture output 3.
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* [9:8] Playback input 0 channel select. 0 = Play output 0.
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* 1 = Play output 1.
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* 2 = Play output 2.
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* 3 = Play output 3.
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* [11:10] Playback input 1 channel select. 0 = Play output 0.
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* 1 = Play output 1.
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* 2 = Play output 2.
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* 3 = Play output 3.
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* [13:12] Playback input 2 channel select. 0 = Play output 0.
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* 1 = Play output 1.
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* 2 = Play output 2.
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* 3 = Play output 3.
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* [15:14] Playback input 3 channel select. 0 = Play output 0.
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* 1 = Play output 1.
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* 2 = Play output 2.
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* 3 = Play output 3.
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* [19:16] Playback mixer output enable. 1 bit per channel.
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* [23:20] Capture mixer output enable. 1 bit per channel.
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* [26:24] FX engine channel capture 0 = 0x60-0x67.
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* 1 = 0x68-0x6f.
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* 2 = 0x70-0x77.
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* 3 = 0x78-0x7f.
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* 4 = 0x80-0x87.
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* 5 = 0x88-0x8f.
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* 6 = 0x90-0x97.
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* 7 = 0x98-0x9f.
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* [31:27] Not used.
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*/
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/* 0x1 = capture on.
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* 0x100 = capture off.
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* 0x200 = capture off.
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* 0x1000 = capture off.
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*/
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#define CAPTURE_RATE_STATUS 0x17 /* Capture sample rate. Read only */
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/* [15:0] Not used.
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* [18:16] Channel 0 Detected sample rate. 0 - 44.1khz
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* 1 - 48 khz
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* 2 - 96 khz
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* 3 - 192 khz
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* 7 - undefined rate.
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* [19] Channel 0. 1 - Valid, 0 - Not Valid.
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* [22:20] Channel 1 Detected sample rate.
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* [23] Channel 1. 1 - Valid, 0 - Not Valid.
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* [26:24] Channel 2 Detected sample rate.
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* [27] Channel 2. 1 - Valid, 0 - Not Valid.
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* [30:28] Channel 3 Detected sample rate.
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* [31] Channel 3. 1 - Valid, 0 - Not Valid.
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*/
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/* 0x18 - 0x1f unused */
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#define PLAYBACK_LAST_SAMPLE 0x20 /* The sample currently being played. Read only */
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/* 0x21 - 0x3f unused */
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#define BASIC_INTERRUPT 0x40 /* Used by both playback and capture interrupt handler */
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/* Playback (0x1<<channel_id) Don't touch high 16bits. */
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/* Capture (0x100<<channel_id). not tested */
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/* Start Playback [3:0] (one bit per channel)
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* Start Capture [11:8] (one bit per channel)
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* Record source select for channel 0 [18:16]
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* Record source select for channel 1 [22:20]
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* Record source select for channel 2 [26:24]
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* Record source select for channel 3 [30:28]
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* 0 - SPDIF channel.
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* 1 - I2S channel.
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* 2 - SRC48 channel.
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* 3 - SRCMulti_SPDIF channel.
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* 4 - SRCMulti_I2S channel.
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* 5 - SPDIF channel.
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* 6 - fxengine capture.
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* 7 - AC97 capture.
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*/
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/* Default 41110000.
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* Writing 0xffffffff hangs the PC.
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* Writing 0xffff0000 -> 77770000 so it must be some sort of route.
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* bit 0x1 starts DMA playback on channel_id 0
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*/
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/* 0x41,42 take values from 0 - 0xffffffff, but have no effect on playback */
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/* 0x43,0x48 do not remember settings */
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/* 0x41-45 unused */
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#define WATERMARK 0x46 /* Test bit to indicate cache level usage */
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/* Values it can have while playing on channel 0.
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* 0000f000, 0000f004, 0000f008, 0000f00c.
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* Readonly.
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*/
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/* 0x47-0x4f unused */
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/* 0x50-0x5f Capture cache data */
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#define SRCSel 0x60 /* SRCSel. Default 0x4. Bypass P16V 0x14 */
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/* [0] 0 = 10K2 audio, 1 = SRC48 mixer output.
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* [2] 0 = 10K2 audio, 1 = SRCMulti SPDIF mixer output.
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* [4] 0 = 10K2 audio, 1 = SRCMulti I2S mixer output.
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*/
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/* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
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/* SRCMulti converts 48khz samples rates to 44.1, 48, 96, 192 to 48. */
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/* SRC48 and SRCMULTI sample rate select and output select. */
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/* 0xffffffff -> 0xC0000015
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* 0xXXXXXXX4 = Enable Front Left/Right
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* Enable PCMs
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*/
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/* 0x61 -> 0x6c are Volume controls */
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#define PLAYBACK_VOLUME_MIXER1 0x61 /* SRC48 Low to mixer input volume control. */
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#define PLAYBACK_VOLUME_MIXER2 0x62 /* SRC48 High to mixer input volume control. */
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#define PLAYBACK_VOLUME_MIXER3 0x63 /* SRCMULTI SPDIF Low to mixer input volume control. */
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#define PLAYBACK_VOLUME_MIXER4 0x64 /* SRCMULTI SPDIF High to mixer input volume control. */
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#define PLAYBACK_VOLUME_MIXER5 0x65 /* SRCMULTI I2S Low to mixer input volume control. */
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#define PLAYBACK_VOLUME_MIXER6 0x66 /* SRCMULTI I2S High to mixer input volume control. */
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#define PLAYBACK_VOLUME_MIXER7 0x67 /* P16V Low to SRCMULTI SPDIF mixer input volume control. */
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#define PLAYBACK_VOLUME_MIXER8 0x68 /* P16V High to SRCMULTI SPDIF mixer input volume control. */
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#define PLAYBACK_VOLUME_MIXER9 0x69 /* P16V Low to SRCMULTI I2S mixer input volume control. */
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/* 0xXXXX3030 = PCM0 Volume (Front).
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* 0x3030XXXX = PCM1 Volume (Center)
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*/
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#define PLAYBACK_VOLUME_MIXER10 0x6a /* P16V High to SRCMULTI I2S mixer input volume control. */
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/* 0x3030XXXX = PCM3 Volume (Rear). */
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#define PLAYBACK_VOLUME_MIXER11 0x6b /* E10K2 Low to SRC48 mixer input volume control. */
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#define PLAYBACK_VOLUME_MIXER12 0x6c /* E10K2 High to SRC48 mixer input volume control. */
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#define SRC48_ENABLE 0x6d /* SRC48 input audio enable */
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/* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
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/* [23:16] The corresponding P16V channel to SRC48 enabled if == 1.
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* [31:24] The corresponding E10K2 channel to SRC48 enabled.
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*/
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#define SRCMULTI_ENABLE 0x6e /* SRCMulti input audio enable. Default 0xffffffff */
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/* SRCMulti converts 48khz samples rates to 44.1, 48, 96, 192 to 48. */
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/* [7:0] The corresponding P16V channel to SRCMulti_I2S enabled if == 1.
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* [15:8] The corresponding E10K2 channel to SRCMulti I2S enabled.
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* [23:16] The corresponding P16V channel to SRCMulti SPDIF enabled.
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* [31:24] The corresponding E10K2 channel to SRCMulti SPDIF enabled.
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*/
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/* Bypass P16V 0xff00ff00
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* Bitmap. 0 = Off, 1 = On.
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* P16V playback outputs:
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* 0xXXXXXXX1 = PCM0 Left. (Front)
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* 0xXXXXXXX2 = PCM0 Right.
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* 0xXXXXXXX4 = PCM1 Left. (Center/LFE)
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* 0xXXXXXXX8 = PCM1 Right.
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* 0xXXXXXX1X = PCM2 Left. (Unknown)
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* 0xXXXXXX2X = PCM2 Right.
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* 0xXXXXXX4X = PCM3 Left. (Rear)
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* 0xXXXXXX8X = PCM3 Right.
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*/
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#define AUDIO_OUT_ENABLE 0x6f /* Default: 000100FF */
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/* [3:0] Does something, but not documented. Probably capture enable.
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* [7:4] Playback channels enable. not documented.
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* [16] AC97 output enable if == 1
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* [30] 0 = SRCMulti_I2S input from fxengine 0x68-0x6f.
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* 1 = SRCMulti_I2S input from SRC48 output.
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* [31] 0 = SRCMulti_SPDIF input from fxengine 0x60-0x67.
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* 1 = SRCMulti_SPDIF input from SRC48 output.
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*/
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/* 0xffffffff -> C00100FF */
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/* 0 -> Not playback sound, irq still running */
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/* 0xXXXXXX10 = PCM0 Left/Right On. (Front)
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* 0xXXXXXX20 = PCM1 Left/Right On. (Center/LFE)
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* 0xXXXXXX40 = PCM2 Left/Right On. (Unknown)
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* 0xXXXXXX80 = PCM3 Left/Right On. (Rear)
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*/
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#define PLAYBACK_SPDIF_SELECT 0x70 /* Default: 12030F00 */
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/* 0xffffffff -> 3FF30FFF */
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/* 0x00000001 pauses stream/irq fail. */
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/* All other bits do not effect playback */
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#define PLAYBACK_SPDIF_SRC_SELECT 0x71 /* Default: 0000E4E4 */
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/* 0xffffffff -> F33FFFFF */
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/* All bits do not effect playback */
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#define PLAYBACK_SPDIF_USER_DATA0 0x72 /* SPDIF out user data 0 */
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#define PLAYBACK_SPDIF_USER_DATA1 0x73 /* SPDIF out user data 1 */
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/* 0x74-0x75 unknown */
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#define CAPTURE_SPDIF_CONTROL 0x76 /* SPDIF in control setting */
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#define CAPTURE_SPDIF_STATUS 0x77 /* SPDIF in status */
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#define CAPURE_SPDIF_USER_DATA0 0x78 /* SPDIF in user data 0 */
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#define CAPURE_SPDIF_USER_DATA1 0x79 /* SPDIF in user data 1 */
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#define CAPURE_SPDIF_USER_DATA2 0x7a /* SPDIF in user data 2 */
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