578 lines
15 KiB
C
578 lines
15 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/interrupt.h>
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#include <alpha/pci/ciareg.h>
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#include <alpha/pci/ciavar.h>
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#include <alpha/isa/isavar.h>
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#include <machine/bwx.h>
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#include <machine/cpuconf.h>
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#include <machine/intr.h>
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#include <machine/intrcnt.h>
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#include <machine/md_var.h>
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#include <machine/resource.h>
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#include <machine/rpb.h>
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#include <machine/sgmap.h>
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#include <machine/swiz.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include "alphapci_if.h"
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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static devclass_t cia_devclass;
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static device_t cia0; /* XXX only one for now */
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static u_int32_t cia_hae_mem;
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static int cia_rev, cia_ispyxis, cia_config;
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struct cia_softc {
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int junk; /* no softc */
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};
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#define CIA_SOFTC(dev) (struct cia_softc*) device_get_softc(dev)
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static alpha_chipset_read_hae_t cia_read_hae;
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static alpha_chipset_write_hae_t cia_write_hae;
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static alpha_chipset_t cia_bwx_chipset = {
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cia_read_hae,
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cia_write_hae,
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};
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static alpha_chipset_t cia_swiz_chipset = {
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cia_read_hae,
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cia_write_hae,
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};
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static u_int32_t
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cia_swiz_set_hae_mem(void *arg, u_int32_t pa)
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{
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/* Only bother with region 1 */
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#define REG1 (7 << 29)
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if ((cia_hae_mem & REG1) != (pa & REG1)) {
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/*
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* Seems fairly paranoid but this is what Linux does...
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*/
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u_int32_t msb = pa & REG1;
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register_t s;
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s = intr_disable();
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cia_hae_mem = (cia_hae_mem & ~REG1) | msb;
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REGVAL(CIA_CSR_HAE_MEM) = cia_hae_mem;
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alpha_mb();
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cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
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intr_restore(s);
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}
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return pa & ~REG1;
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}
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static u_int64_t
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cia_read_hae(void)
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{
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return cia_hae_mem & REG1;
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}
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static void
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cia_write_hae(u_int64_t hae)
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{
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u_int32_t pa = hae;
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cia_swiz_set_hae_mem(0, pa);
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}
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static int cia_probe(device_t dev);
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static int cia_attach(device_t dev);
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static int cia_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags,
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driver_intr_t *intr, void *arg, void **cookiep);
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static int cia_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie);
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static device_method_t cia_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, cia_probe),
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DEVMETHOD(device_attach, cia_attach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_setup_intr, cia_setup_intr),
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DEVMETHOD(bus_teardown_intr, cia_teardown_intr),
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{ 0, 0 }
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};
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static driver_t cia_driver = {
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"cia",
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cia_methods,
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sizeof(struct cia_softc),
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};
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#define CIA_SGMAP_BASE (8*1024*1024)
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#define CIA_SGMAP_SIZE (8*1024*1024)
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#define CIA_PYXIS_BUG_BASE (128*1024*1024)
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#define CIA_PYXIS_BUG_SIZE (2*1024*1024)
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static void
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cia_sgmap_invalidate(void)
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{
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REGVAL(CIA_PCI_TBIA) = CIA_PCI_TBIA_ALL;
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alpha_mb();
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}
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static void
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cia_sgmap_invalidate_pyxis(void)
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{
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volatile u_int64_t dummy;
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u_int32_t ctrl;
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int i;
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register_t s;
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s = intr_disable();
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/*
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* Put the Pyxis into PCI loopback mode.
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*/
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alpha_mb();
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ctrl = REGVAL(CIA_CSR_CTRL);
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REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
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alpha_mb();
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/*
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* Now, read from PCI dense memory space at offset 128M (our
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* target window base), skipping 64k on each read. This forces
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* S/G TLB misses.
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*
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* XXX Looks like the TLB entries are `not quite LRU'. We need
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* XXX to read more times than there are actual tags!
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*/
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for (i = 0; i < CIA_TLB_NTAGS + 4; i++) {
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dummy = *((volatile u_int64_t *)
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ALPHA_PHYS_TO_K0SEG(CIA_PCI_DENSE + CIA_PYXIS_BUG_BASE +
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(i * 65536)));
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}
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/*
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* Restore normal PCI operation.
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*/
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alpha_mb();
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REGVAL(CIA_CSR_CTRL) = ctrl;
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alpha_mb();
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intr_restore(s);
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}
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static void
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cia_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
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{
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u_int64_t *sgtable = arg;
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int index = alpha_btop(ba - CIA_SGMAP_BASE);
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if (pa) {
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if (pa > (1L<<32))
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panic("cia_sgmap_map: can't map address 0x%lx", pa);
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sgtable[index] = ((pa >> 13) << 1) | 1;
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} else {
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sgtable[index] = 0;
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}
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alpha_mb();
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if (cia_ispyxis)
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cia_sgmap_invalidate_pyxis();
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else
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cia_sgmap_invalidate();
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}
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static void
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cia_init_sgmap(void)
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{
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void *sgtable;
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/*
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* First setup Window 0 to map 8Mb to 16Mb with an
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* sgmap. Allocate the map aligned to a 32k boundary.
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*/
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REGVAL(CIA_PCI_W0BASE) = (CIA_SGMAP_BASE
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| CIA_PCI_WnBASE_SG_EN
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| CIA_PCI_WnBASE_W_EN);
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alpha_mb();
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REGVAL(CIA_PCI_W0MASK) = CIA_PCI_WnMASK_8M;
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alpha_mb();
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sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
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0, (1L<<34),
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32*1024, (1L<<34));
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if (!sgtable)
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panic("cia_init_sgmap: can't allocate page table");
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REGVAL(CIA_PCI_T0BASE) =
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(pmap_kextract((vm_offset_t) sgtable) >> CIA_PCI_TnBASE_SHIFT);
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chipset.sgmap = sgmap_map_create(CIA_SGMAP_BASE,
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CIA_SGMAP_BASE + CIA_SGMAP_SIZE - 1,
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cia_sgmap_map, sgtable);
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if (cia_ispyxis) {
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/*
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* Pyxis has broken TLB invalidate. We use the NetBSD
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* workaround of using another region to spill entries
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* out of the TLB. The 'bug' region is 2Mb mapped at
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* 128Mb.
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*/
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int i;
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vm_offset_t pa;
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u_int64_t *bugtable;
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REGVAL(CIA_PCI_W2BASE) = CIA_PYXIS_BUG_BASE |
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CIA_PCI_WnBASE_SG_EN | CIA_PCI_WnBASE_W_EN;
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alpha_mb();
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REGVAL(CIA_PCI_W2MASK) = CIA_PCI_WnMASK_2M;
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alpha_mb();
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bugtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
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0, (1L<<34),
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2*1024, (1L<<34));
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if (!bugtable)
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panic("cia_init_sgmap: can't allocate page table");
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REGVAL(CIA_PCI_T2BASE) =
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(pmap_kextract((vm_offset_t) bugtable)
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>> CIA_PCI_TnBASE_SHIFT);
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pa = sgmap_overflow_page();
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for (i = 0; i < alpha_btop(CIA_PYXIS_BUG_SIZE); i++)
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bugtable[i] = ((pa >> 13) << 1) | 1;
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}
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}
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void
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cia_init()
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{
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static int initted = 0;
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static union space {
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struct bwx_space bwx;
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struct swiz_space swiz;
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} io_space, mem_space;
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if (initted) return;
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initted = 1;
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if (chipset_bwx == 0) {
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swiz_init_space(&io_space.swiz, KV(CIA_PCI_SIO1));
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swiz_init_space_hae(&mem_space.swiz, KV(CIA_PCI_SMEM1),
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cia_swiz_set_hae_mem, 0);
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chipset = cia_swiz_chipset;
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} else {
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bwx_init_space(&io_space.bwx, KV(CIA_EV56_BWIO));
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bwx_init_space(&mem_space.bwx, KV(CIA_EV56_BWMEM));
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chipset = cia_bwx_chipset;
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}
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cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
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busspace_isa_io = (struct alpha_busspace *) &io_space;
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busspace_isa_mem = (struct alpha_busspace *) &mem_space;
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if (platform.pci_intr_init)
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platform.pci_intr_init();
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}
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static int
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cia_probe(device_t dev)
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{
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uintptr_t use_bwx = 1;
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device_t child;
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if (cia0)
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return ENXIO;
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cia0 = dev;
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device_set_desc(dev, "2117x Core Logic chipset"); /* XXX */
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isa_init_intr();
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cia_rev = REGVAL(CIA_CSR_REV) & REV_MASK;
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/*
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* Determine if we have a Pyxis. Only two systypes can
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* have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX)
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* and the DEC_ST550 systype (Miata).
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*/
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if ((hwrpb->rpb_type == ST_EB164 &&
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(hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) ||
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hwrpb->rpb_type == ST_DEC_550)
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cia_ispyxis = TRUE;
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else
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cia_ispyxis = FALSE;
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cia_init_sgmap();
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/*
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* ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register.
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*/
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if (cia_rev >= 2 || cia_ispyxis)
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cia_config = REGVAL(CIA_CSR_CNFG);
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else
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cia_config = 0;
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if ((alpha_implver() < ALPHA_IMPLVER_EV5) ||
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(alpha_amask(ALPHA_AMASK_BWX) != 0) ||
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(cia_config & CNFG_BWEN) == 0) {
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use_bwx = 0;
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} else {
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use_bwx = 1;
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}
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if (cia_ispyxis) {
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if (use_bwx == 0) {
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printf("PYXIS but not BWX?\n");
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}
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}
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child = device_add_child(dev, "pcib", 0);
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chipset_bwx = use_bwx = (use_bwx == (uintptr_t) 1);
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device_set_ivars(child, (void *)use_bwx);
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return 0;
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}
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static int
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cia_attach(device_t dev)
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{
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char* name;
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int pass;
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cia_init();
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name = cia_ispyxis ? "Pyxis" : "ALCOR/ALCOR2";
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if (cia_ispyxis) {
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name = "Pyxis";
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pass = cia_rev;
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} else {
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name = "ALCOR/ALCOR2";
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pass = cia_rev+1;
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}
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printf("cia0: %s, pass %d\n", name, pass);
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if (cia_config)
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printf("cia0: extended capabilities: %b\n",
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cia_config, CIA_CSR_CNFG_BITS);
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#ifdef DEC_ST550
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if (hwrpb->rpb_type == ST_DEC_550 &&
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(hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
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/*
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* Miata 1 systems have a bug: DMA cannot cross
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* an 8k boundary! Make sure PCI read prefetching
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* is disabled on these chips. Note that secondary
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* PCI busses don't have this problem, because of
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* the way PPBs handle PCI read requests.
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*
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* In the 21174 Technical Reference Manual, this is
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* actually documented as "Pyxis Pass 1", but apparently
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* there are chips that report themselves as "Pass 1"
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* which do not have the bug! Miatas with the Cypress
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* PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not
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* have the bug, so we use this check.
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*
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* XXX We also need to deal with this boundary constraint
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* XXX in the PCI bus 0 (and ISA) DMA tags, but some
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* XXX drivers are going to need to be changed first.
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*/
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u_int32_t ctrl;
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/* XXX no bets... */
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printf("cia0: WARNING: Pyxis pass 1 DMA bug; no bets...\n");
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alpha_mb();
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ctrl = REGVAL(CIA_CSR_CTRL);
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ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE);
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REGVAL(CIA_CSR_CTRL) = ctrl;
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alpha_mb();
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}
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#endif
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if (!platform.iointr) /* XXX */
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set_iointr(alpha_dispatch_intr);
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if (chipset_bwx) {
|
|
snprintf(chipset_type, sizeof(chipset_type), "cia/bwx");
|
|
chipset_bwx = 1;
|
|
chipset_ports = CIA_EV56_BWIO;
|
|
chipset_memory = CIA_EV56_BWMEM;
|
|
chipset_dense = CIA_PCI_DENSE;
|
|
} else {
|
|
snprintf(chipset_type, sizeof(chipset_type), "cia/swiz");
|
|
chipset_bwx = 0;
|
|
chipset_ports = CIA_PCI_SIO1;
|
|
chipset_memory = CIA_PCI_SMEM1;
|
|
chipset_dense = CIA_PCI_DENSE;
|
|
chipset_hae_mask = 7L << 29;
|
|
}
|
|
|
|
bus_generic_attach(dev);
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
cia_disable_intr(uintptr_t vector)
|
|
{
|
|
int irq;
|
|
|
|
irq = (vector - 0x900) >> 4;
|
|
mtx_lock_spin(&icu_lock);
|
|
platform.pci_intr_disable(irq);
|
|
mtx_unlock_spin(&icu_lock);
|
|
}
|
|
|
|
static void
|
|
cia_enable_intr(uintptr_t vector)
|
|
{
|
|
int irq;
|
|
|
|
irq = (vector - 0x900) >> 4;
|
|
mtx_lock_spin(&icu_lock);
|
|
platform.pci_intr_enable(irq);
|
|
mtx_unlock_spin(&icu_lock);
|
|
}
|
|
|
|
static int
|
|
cia_setup_intr(device_t dev, device_t child,
|
|
struct resource *irq, int flags,
|
|
driver_intr_t *intr, void *arg, void **cookiep)
|
|
{
|
|
int error;
|
|
|
|
error = rman_activate_resource(irq);
|
|
if (error)
|
|
return error;
|
|
|
|
error = alpha_setup_intr(
|
|
device_get_nameunit(child ? child : dev),
|
|
0x900 + (irq->r_start << 4), intr, arg, flags, cookiep,
|
|
&intrcnt[INTRCNT_EB164_IRQ + irq->r_start],
|
|
cia_disable_intr, cia_enable_intr);
|
|
if (error)
|
|
return error;
|
|
|
|
/* Enable PCI interrupt */
|
|
mtx_lock_spin(&icu_lock);
|
|
platform.pci_intr_enable(irq->r_start);
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
device_printf(child, "interrupting at CIA irq %d\n",
|
|
(int) irq->r_start);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
cia_teardown_intr(device_t dev, device_t child,
|
|
struct resource *irq, void *cookie)
|
|
{
|
|
alpha_teardown_intr(cookie);
|
|
return rman_deactivate_resource(irq);
|
|
}
|
|
|
|
DRIVER_MODULE(cia, root, cia_driver, cia_devclass, 0, 0);
|