f75615f26f
drivers. The BMIPS32/BMIPS3300 cores use a register layout distinct from the MIPS74K core, and are only found on siba(4) devices. Reviewed by: mizhka Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D7791
191 lines
5.9 KiB
C
191 lines
5.9 KiB
C
/*-
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* Copyright 2000,2001,2002,2003 Broadcom Corporation.
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* All rights reserved.
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*
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* This file is derived from the sbmips32.h header distributed
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* by Broadcom with the CFE 1.4.2 sources.
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*
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* This software is furnished under license and may be used and
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* copied only in accordance with the following terms and
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* conditions. Subject to these conditions, you may download,
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* copy, install, use, modify and distribute modified or unmodified
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* copies of this software in source and/or binary form. No title
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* or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce
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* and retain this copyright notice and list of conditions
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* as they appear in the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or
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* logo of Broadcom Corporation. The "Broadcom Corporation"
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* name may not be used to endorse or promote products derived
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* from this software without the prior written permission of
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* Broadcom Corporation.
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*
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* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
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* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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* PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
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* SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
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* PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* *********************************************************************
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* Broadcom Common Firmware Environment (CFE)
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*
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* MIPS32 CPU definitions File: sbmips32.h
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*
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* This module contains constants and macros specific to the
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* Broadcom MIPS32 core. In addition to generic MIPS32, it
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* includes definitions for the MIP32-01 and MIPS3302 OCP cores
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* for the Silicon Backplane.
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*
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*********************************************************************/
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#ifndef _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
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#define _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
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#include <machine/cpufunc.h>
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/*
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* The following Broadcom Custom CP0 Registers appear in the Broadcom
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* BMIPS330x MIPS32 core.
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*/
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#define BMIPS_COP_0_BCMCFG 22
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/*
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* Custom CP0 Accessors
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*/
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#define BCM_BMIPS_RW32_COP0_SEL(n,r,s) \
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static __inline uint32_t \
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bcm_bmips_rd_ ## n(void) \
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{ \
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int v0; \
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__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
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: [v0] "=&r"(v0)); \
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mips_barrier(); \
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return (v0); \
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} \
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static __inline void \
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bcm_bmips_wr_ ## n(uint32_t a0) \
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{ \
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__asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
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__XSTRING(COP0_SYNC)";" \
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"nop;" \
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"nop;" \
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: \
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: [a0] "r"(a0)); \
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mips_barrier(); \
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} struct __hack
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BCM_BMIPS_RW32_COP0_SEL(pllcfg1, MIPS_COP_0_CONFIG, 1);
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BCM_BMIPS_RW32_COP0_SEL(pllcfg2, MIPS_COP_0_CONFIG, 2);
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BCM_BMIPS_RW32_COP0_SEL(clksync, MIPS_COP_0_CONFIG, 3);
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BCM_BMIPS_RW32_COP0_SEL(pllcfg3, MIPS_COP_0_CONFIG, 4);
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BCM_BMIPS_RW32_COP0_SEL(rstcfg, MIPS_COP_0_CONFIG, 5);
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/*
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* Broadcom PLLConfig1 Register (22, select 1)
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*/
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/* SoftMIPSPLLCfg */
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#define BMIPS_BCMCFG_PLLCFG1_MC_SHIFT 10
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#define BMIPS_BCMCFG_PLLCFG1_MC_MASK 0xFFFFFC00
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/* SoftISBPLLCfg */
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#define BMIPS_BCMCFG_PLLCFG1_BC_SHIFT 5
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#define BMIPS_BCMCFG_PLLCFG1_BC_MASK 0x000003E0
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/* SoftRefPLLCfg */
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#define BMIPS_BCMCFG_PLLCFG1_PC_SHIFT 0
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#define BMIPS_BCMCFG_PLLCFG1_PC_MASK 0x0000001F
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/*
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* Broadcom PLLConfig2 Register (22, select 2)
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*/
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/* Soft1to1ClkRatio */
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#define BMIPS_BCMCFG_PLLCFG2_CR (1<<23)
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/* SoftUSBxPLLCfg */
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#define BMIPS_BCMCFG_PLLCFG2_UC_SHIFT 15
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#define BMIPS_BCMCFG_PLLCFG2_UC_MASK 0x007F8000
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/* SoftIDExPLLCfg */
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#define BMIPS_BCMCFG_PLLCFG2_IC_SHIFT 7
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#define BMIPS_BCMCFG_PLLCFG2_IC_MASK 0x00007F80
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#define BMIPS_BCMCFG_PLLCFG2_BE (1<<6) /* ISBxSoftCfgEnable */
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#define BMIPS_BCMCFG_PLLCFG2_UE (1<<5) /* USBxSoftCfgEnable */
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#define BMIPS_BCMCFG_PLLCFG2_IE (1<<4) /* IDExSoftCfgEnable */
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#define BMIPS_BCMCFG_PLLCFG2_CA (1<<3) /* CfgActive */
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#define BMIPS_BCMCFG_PLLCFG2_CF (1<<2) /* RefSoftCfgEnable */
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#define BMIPS_BCMCFG_PLLCFG2_CI (1<<1) /* ISBSoftCfgEnable */
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#define BMIPS_BCMCFG_PLLCFG2_CC (1<<0) /* MIPSSoftCfgEnable */
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/*
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* Broadcom ClkSync Register (22, select 3)
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*/
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/* SoftClkCfgHigh */
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#define BMIPS_BCMCFG_CLKSYNC_CH_SHIFT 16
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#define BMIPS_BCMCFG_CLKSYNC_CH_MASK 0xFFFF0000
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/* SoftClkCfgLow */
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#define BMIPS_BCMCFG_CLKSYNC_CL_SHIFT 0
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#define BMIPS_BCMCFG_CLKSYNC_CL_MASK 0x0000FFFF
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/*
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* Broadcom ISBxPLLConfig3 Register (22, select 4)
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*/
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/* AsyncClkRatio */
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#define BMIPS_BCMCFG_PLLCFG3_AR_SHIFT 23
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#define BMIPS_BCMCFG_PLLCFG3_AR_MASK 0x01800000
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#define BMIPS_BCMCFG_PLLCFG3_SM (1<<22) /* SyncMode */
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/* SoftISBxPLLCfg */
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#define BMIPS_BCMCFG_PLLCFG3_IC_SHIFT 0
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#define BMIPS_BCMCFG_PLLCFG3_IC_MASK 0x003FFFFF
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/*
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* Broadcom BRCMRstConfig Register (22, select 5)
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*/
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#define BMIPS_BCMCFG_RSTCFG_SR (1<<18) /* SSMR */
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#define BMIPS_BCMCFG_RSTCFG_DT (1<<16) /* BHTD */
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/* RStSt */
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#define BMIPS_BCMCFG_RSTCFG_RS_SHIFT 8
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#define BMIPS_BCMCFG_RSTCFG_RS_MASK 0x00001F00
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#define BMIPS_BCMCFG_RST_OTHER 0x00
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#define BMIPS_BCMCFG_RST_SH 0x01
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#define BMIPS_BCMCFG_RST_SS 0x02
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#define BMIPS_BCMCFG_RST_EJTAG 0x04
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#define BMIPS_BCMCFG_RST_WDOG 0x08
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#define BMIPS_BCMCFG_RST_CRC 0x10
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#define BMIPS_BCMCFG_RSTCFG_CR (1<<7) /* RStCr */
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/* WBMD */
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#define BMIPS_BCMCFG_RSTCFG_WD_SHIFT 3
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#define BMIPS_BCMCFG_RSTCFG_WD_MASK 0x00000078
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#define BMIPS_BCMCFG_RSTCFG_SS (1<<2) /* SSR */
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#define BMIPS_BCMCFG_RSTCFG_SH (1<<1) /* SHR */
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#define BMIPS_BCMCFG_RSTCFG_BR (1<<0) /* BdR */
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#endif /* _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_ */
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