61bc42f782
TI OMAP controllers which will return the reset-in-progress bit as zero if you read the status register too fast after setting the reset bit. The zero is apparently from a stale snapshot of the internal state presented in the interface register, and leads to a false indication that the reset is complete when it either hasn't started yet or is in-progress. The workaround is to first loop until the bit is seen as asserted, then do the normal loop waiting to see it de-asserted. Submitted by: Michal Meloun <meloun@miracle.cz> |
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allwinner | ||
altera/socfpga | ||
arm | ||
at91 | ||
broadcom/bcm2835 | ||
cavium/cns11xx | ||
conf | ||
freescale | ||
include | ||
lpc | ||
mv | ||
rockchip | ||
samsung | ||
ti | ||
versatile | ||
xilinx | ||
xscale |