fdb59f927e
dependencies. A 'struct pmc_classdep' structure describes operations on PMCs; 'struct pmc_mdep' contains one or more 'struct pmc_classdep' structures depending on the CPU in question. Inside PMC class dependent code, row indices are relative to the PMCs supported by the PMC class; MI code in "hwpmc_mod.c" translates global row indices before invoking class dependent operations. - Augment the OP_GETCPUINFO request with the number of PMCs present in a PMC class. - Move code common to Intel CPUs to file "hwpmc_intel.c". - Move TSC handling to file "hwpmc_tsc.c".
98 lines
3.3 KiB
C
98 lines
3.3 KiB
C
/*-
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* Copyright (c) 2005, Joseph Koshy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* Machine dependent interfaces */
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#ifndef _DEV_HWPMC_AMD_H_
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#define _DEV_HWPMC_AMD_H_ 1
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/* AMD K7 and K8 PMCs */
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#define AMD_PMC_EVSEL_0 0xC0010000
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#define AMD_PMC_EVSEL_1 0xC0010001
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#define AMD_PMC_EVSEL_2 0xC0010002
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#define AMD_PMC_EVSEL_3 0xC0010003
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#define AMD_PMC_PERFCTR_0 0xC0010004
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#define AMD_PMC_PERFCTR_1 0xC0010005
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#define AMD_PMC_PERFCTR_2 0xC0010006
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#define AMD_PMC_PERFCTR_3 0xC0010007
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#define AMD_NPMCS 4
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#define AMD_PMC_COUNTERMASK 0xFF000000
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#define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK)
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#define AMD_PMC_INVERT (1 << 23)
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#define AMD_PMC_ENABLE (1 << 22)
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#define AMD_PMC_INT (1 << 20)
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#define AMD_PMC_PC (1 << 19)
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#define AMD_PMC_EDGE (1 << 18)
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#define AMD_PMC_OS (1 << 17)
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#define AMD_PMC_USR (1 << 16)
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#define AMD_PMC_UNITMASK_M 0x10
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#define AMD_PMC_UNITMASK_O 0x08
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#define AMD_PMC_UNITMASK_E 0x04
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#define AMD_PMC_UNITMASK_S 0x02
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#define AMD_PMC_UNITMASK_I 0x01
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#define AMD_PMC_UNITMASK_MOESI 0x1F
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#define AMD_PMC_UNITMASK 0xFF00
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#define AMD_PMC_EVENTMASK 0x00FF
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#define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK)
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#define AMD_PMC_TO_EVENTMASK(x) ((x) & 0xFF)
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#define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \
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AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \
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AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK)
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#define AMD_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
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PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | \
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PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER)
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#define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0)
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#define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0)
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#define AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (-(V))
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#define AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P))
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struct pmc_md_amd_op_pmcallocate {
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uint32_t pm_amd_config;
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};
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#ifdef _KERNEL
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/* MD extension for 'struct pmc' */
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struct pmc_md_amd_pmc {
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uint32_t pm_amd_evsel;
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};
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#endif /* _KERNEL */
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#endif /* _DEV_HWPMC_AMD_H_ */
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