d3810ff91c
The datasheets refer to this controller as EMAC, not to be confused with the fast ethernet controller (also named EMAC) found in A10/A20 SoCs. Tested on a BananaPi M3 (A83T), which uses an external RGMII PHY (RTL8211E). Reviewed by: adrian Differential Revision: https://reviews.freebsd.org/D6169
182 lines
5.6 KiB
C
182 lines
5.6 KiB
C
/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Allwinner Gigabit Ethernet
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*/
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#ifndef __IF_AWGREG_H__
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#define __IF_AWGREG_H__
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#define EMAC_BASIC_CTL_0 0x00
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#define BASIC_CTL_SPEED (0x3 << 2)
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#define BASIC_CTL_SPEED_SHIFT 2
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#define BASIC_CTL_SPEED_1000 0
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#define BASIC_CTL_SPEED_10 2
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#define BASIC_CTL_SPEED_100 3
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#define BASIC_CTL_LOOPBACK (1 << 1)
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#define BASIC_CTL_DUPLEX (1 << 0)
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#define EMAC_BASIC_CTL_1 0x04
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#define BASIC_CTL_BURST_LEN (0x3f << 24)
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#define BASIC_CTL_BURST_LEN_SHIFT 24
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#define BASIC_CTL_RX_TX_PRI (1 << 1)
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#define BASIC_CTL_SOFT_RST (1 << 0)
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#define EMAC_INT_STA 0x08
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#define RX_BUF_UA_INT (1 << 10)
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#define RX_INT (1 << 8)
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#define TX_UNDERFLOW_INT (1 << 4)
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#define TX_BUF_UA_INT (1 << 2)
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#define TX_DMA_STOPPED_INT (1 << 1)
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#define TX_INT (1 << 0)
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#define EMAC_INT_EN 0x0c
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#define RX_BUF_UA_INT_EN (1 << 10)
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#define RX_INT_EN (1 << 8)
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#define TX_UNDERFLOW_INT_EN (1 << 4)
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#define TX_BUF_UA_INT_EN (1 << 2)
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#define TX_DMA_STOPPED_INT_EN (1 << 1)
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#define TX_INT_EN (1 << 0)
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#define EMAC_TX_CTL_0 0x10
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#define TX_EN (1 << 31)
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#define EMAC_TX_CTL_1 0x14
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#define TX_DMA_START (1 << 31)
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#define TX_DMA_EN (1 << 30)
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#define TX_MD (1 << 1)
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#define FLUSH_TX_FIFO (1 << 0)
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#define EMAC_TX_FLOW_CTL 0x1c
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#define PAUSE_TIME (0xffff << 4)
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#define PAUSE_TIME_SHIFT 4
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#define TX_FLOW_CTL_EN (1 << 0)
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#define EMAC_TX_DMA_LIST 0x20
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#define EMAC_RX_CTL_0 0x24
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#define RX_EN (1 << 31)
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#define JUMBO_FRM_EN (1 << 29)
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#define STRIP_FCS (1 << 28)
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#define CHECK_CRC (1 << 27)
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#define RX_FLOW_CTL_EN (1 << 16)
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#define EMAC_RX_CTL_1 0x28
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#define RX_DMA_START (1 << 31)
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#define RX_DMA_EN (1 << 30)
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#define RX_MD (1 << 1)
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#define EMAC_RX_DMA_LIST 0x34
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#define EMAC_RX_FRM_FLT 0x38
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#define DIS_ADDR_FILTER (1 << 31)
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#define DIS_BROADCAST (1 << 17)
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#define RX_ALL_MULTICAST (1 << 16)
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#define CTL_FRM_FILTER (0x3 << 12)
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#define CTL_FRM_FILTER_SHIFT 12
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#define HASH_MULTICAST (1 << 9)
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#define HASH_UNICAST (1 << 8)
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#define SA_FILTER_EN (1 << 6)
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#define SA_INV_FILTER (1 << 5)
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#define DA_INV_FILTER (1 << 4)
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#define FLT_MD (1 << 1)
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#define RX_ALL (1 << 0)
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#define EMAC_RX_HASH_0 0x40
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#define EMAC_RX_HASH_1 0x44
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#define EMAC_MII_CMD 0x48
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#define MDC_DIV_RATIO_M (0x7 << 20)
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#define MDC_DIV_RATIO_M_16 0
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#define MDC_DIV_RATIO_M_32 1
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#define MDC_DIV_RATIO_M_64 2
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#define MDC_DIV_RATIO_M_128 3
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#define MDC_DIV_RATIO_M_SHIFT 20
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#define PHY_ADDR (0x1f << 12)
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#define PHY_ADDR_SHIFT 12
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#define PHY_REG_ADDR (0x1f << 4)
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#define PHY_REG_ADDR_SHIFT 4
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#define MII_WR (1 << 1)
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#define MII_BUSY (1 << 0)
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#define EMAC_MII_DATA 0x4c
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#define EMAC_ADDR_HIGH(n) (0x50 + (n) * 8)
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#define EMAC_ADDR_LOW(n) (0x54 + (n) * 8)
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#define EMAC_TX_DMA_STA 0x80
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#define EMAC_TX_DMA_CUR_DESC 0x84
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#define EMAC_TX_DMA_CUR_BUF 0x88
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#define EMAC_RX_DMA_STA 0xc0
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#define EMAC_RX_DMA_CUR_DESC 0xc4
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#define EMAC_RX_DMA_CUR_BUF 0xc8
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#define EMAC_RGMII_STA 0xd0
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struct emac_desc {
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uint32_t status;
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/* Transmit */
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#define TX_DESC_CTL (1 << 31)
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#define TX_HEADER_ERR (1 << 16)
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#define TX_LENGTH_ERR (1 << 14)
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#define TX_PAYLOAD_ERR (1 << 12)
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#define TX_CRS_ERR (1 << 10)
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#define TX_COL_ERR_0 (1 << 9)
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#define TX_COL_ERR_1 (1 << 8)
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#define TX_COL_CNT (0xf << 3)
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#define TX_COL_CNT_SHIFT 3
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#define TX_DEFER_ERR (1 << 2)
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#define TX_UNDERFLOW_ERR (1 << 1)
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#define TX_DEFER (1 << 0)
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/* Receive */
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#define RX_DESC_CTL (1 << 31)
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#define RX_DAF_FAIL (1 << 30)
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#define RX_FRM_LEN (0x3fff << 16)
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#define RX_FRM_LEN_SHIFT 16
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#define RX_NO_ENOUGH_BUF_ERR (1 << 14)
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#define RX_SAF_FAIL (1 << 13)
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#define RX_OVERFLOW_ERR (1 << 11)
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#define RX_FIR_DESC (1 << 9)
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#define RX_LAST_DESC (1 << 8)
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#define RX_HEADER_ERR (1 << 7)
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#define RX_COL_ERR (1 << 6)
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#define RX_FRM_TYPE (1 << 5)
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#define RX_LENGTH_ERR (1 << 4)
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#define RX_PHY_ERR (1 << 3)
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#define RX_CRC_ERR (1 << 1)
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#define RX_PAYLOAD_ERR (1 << 0)
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uint32_t size;
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/* Transmit */
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#define TX_INT_CTL (1 << 31)
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#define TX_LAST_DESC (1 << 30)
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#define TX_FIR_DESC (1 << 29)
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#define TX_CHECKSUM_CTL (0x3 << 27)
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#define TX_CHECKSUM_CTL_IP 1
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#define TX_CHECKSUM_CTL_NO_PSE 2
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#define TX_CHECKSUM_CTL_FULL 3
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#define TX_CHECKSUM_CTL_SHIFT 27
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#define TX_CRC_CTL (1 << 26)
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#define TX_BUF_SIZE (0xfff << 0)
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#define TX_BUF_SIZE_SHIFT 0
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/* Receive */
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#define RX_INT_CTL (1 << 31)
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#define RX_BUF_SIZE (0xfff << 0)
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#define RX_BUF_SIZE_SHIFT 0
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uint32_t addr;
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uint32_t next;
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} __packed;
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#endif /* !__IF_AWGREG_H__ */
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