19d3b47b92
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
397 lines
12 KiB
C
397 lines
12 KiB
C
/* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause
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*
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* Copyright (c) 2002-2004 Juli Mallett. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Per Fogelstrom.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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#include <sys/types.h>
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#include <machine/cpuregs.h>
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/*
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* These functions are required by user-land atomi ops
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*/
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static __inline void
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mips_barrier(void)
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{
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#if defined(CPU_CNMIPS) || defined(CPU_RMI) || defined(CPU_NLM)
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__compiler_membar();
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#else
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__asm __volatile (".set noreorder\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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".set reorder\n\t"
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: : : "memory");
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#endif
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}
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static __inline void
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mips_cp0_sync(void)
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{
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__asm __volatile (__XSTRING(COP0_SYNC));
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}
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static __inline void
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mips_wbflush(void)
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{
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#if defined(CPU_CNMIPS)
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__asm __volatile (".set noreorder\n\t"
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"syncw\n\t"
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".set reorder\n"
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: : : "memory");
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#else
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__asm __volatile ("sync" : : : "memory");
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mips_barrier();
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#endif
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}
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#ifdef _KERNEL
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/*
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* XXX
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* It would be nice to add variants that read/write register_t, to avoid some
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* ABI checks.
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*/
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#if defined(__mips_n32) || defined(__mips_n64)
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#define MIPS_RW64_COP0(n,r) \
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static __inline uint64_t \
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mips_rd_ ## n (void) \
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{ \
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int v0; \
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__asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \
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: [v0] "=&r"(v0)); \
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mips_barrier(); \
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return (v0); \
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} \
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static __inline void \
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mips_wr_ ## n (uint64_t a0) \
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{ \
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__asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \
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__XSTRING(COP0_SYNC)";" \
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"nop;" \
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"nop;" \
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: \
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: [a0] "r"(a0)); \
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mips_barrier(); \
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} struct __hack
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#define MIPS_RW64_COP0_SEL(n,r,s) \
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static __inline uint64_t \
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mips_rd_ ## n(void) \
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{ \
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int v0; \
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__asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
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: [v0] "=&r"(v0)); \
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mips_barrier(); \
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return (v0); \
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} \
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static __inline void \
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mips_wr_ ## n(uint64_t a0) \
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{ \
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__asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
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__XSTRING(COP0_SYNC)";" \
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: \
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: [a0] "r"(a0)); \
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mips_barrier(); \
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} struct __hack
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#if defined(__mips_n64)
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MIPS_RW64_COP0(excpc, MIPS_COP_0_EXC_PC);
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MIPS_RW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
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MIPS_RW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
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MIPS_RW64_COP0_SEL(userlocal, MIPS_COP_0_USERLOCAL, 2);
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#ifdef CPU_CNMIPS
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MIPS_RW64_COP0_SEL(cvmcount, MIPS_COP_0_COUNT, 6);
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MIPS_RW64_COP0_SEL(cvmctl, MIPS_COP_0_COUNT, 7);
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MIPS_RW64_COP0_SEL(cvmmemctl, MIPS_COP_0_COMPARE, 7);
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MIPS_RW64_COP0_SEL(icache_err, MIPS_COP_0_CACHE_ERR, 0);
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MIPS_RW64_COP0_SEL(dcache_err, MIPS_COP_0_CACHE_ERR, 1);
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#endif
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#endif
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#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
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MIPS_RW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
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MIPS_RW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
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#endif
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MIPS_RW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
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#undef MIPS_RW64_COP0
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#undef MIPS_RW64_COP0_SEL
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#endif
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#define MIPS_RW32_COP0(n,r) \
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static __inline uint32_t \
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mips_rd_ ## n (void) \
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{ \
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int v0; \
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__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \
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: [v0] "=&r"(v0)); \
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mips_barrier(); \
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return (v0); \
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} \
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static __inline void \
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mips_wr_ ## n (uint32_t a0) \
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{ \
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__asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \
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__XSTRING(COP0_SYNC)";" \
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"nop;" \
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"nop;" \
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: \
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: [a0] "r"(a0)); \
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mips_barrier(); \
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} struct __hack
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#define MIPS_RW32_COP0_SEL(n,r,s) \
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static __inline uint32_t \
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mips_rd_ ## n(void) \
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{ \
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int v0; \
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__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
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: [v0] "=&r"(v0)); \
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mips_barrier(); \
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return (v0); \
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} \
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static __inline void \
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mips_wr_ ## n(uint32_t a0) \
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{ \
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__asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
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__XSTRING(COP0_SYNC)";" \
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"nop;" \
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"nop;" \
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: \
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: [a0] "r"(a0)); \
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mips_barrier(); \
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} struct __hack
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#ifdef CPU_CNMIPS
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static __inline void mips_sync_icache (void)
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{
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__asm __volatile (
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".set push\n"
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".set mips64\n"
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".word 0x041f0000\n" /* xxx ICACHE */
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"nop\n"
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".set pop\n"
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: : );
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}
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#endif
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MIPS_RW32_COP0(compare, MIPS_COP_0_COMPARE);
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MIPS_RW32_COP0(config, MIPS_COP_0_CONFIG);
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MIPS_RW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1);
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MIPS_RW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2);
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MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3);
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#ifdef CPU_CNMIPS
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MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4);
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#endif
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#ifdef BERI_LARGE_TLB
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MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5);
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#endif
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#if defined(CPU_NLM) || defined(BERI_LARGE_TLB)
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MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
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#endif
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#if defined(CPU_NLM) || defined(CPU_MIPS1004K) || defined (CPU_MIPS74K) || \
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defined(CPU_MIPS24K)
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MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
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#endif
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MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
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MIPS_RW32_COP0(index, MIPS_COP_0_TLB_INDEX);
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MIPS_RW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
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MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE);
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#if !defined(__mips_n64)
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MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC);
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#endif
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MIPS_RW32_COP0(status, MIPS_COP_0_STATUS);
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MIPS_RW32_COP0_SEL(cmgcrbase, 15, 3);
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/* XXX: Some of these registers are specific to MIPS32. */
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#if !defined(__mips_n64)
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MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
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MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
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MIPS_RW32_COP0_SEL(userlocal, MIPS_COP_0_USERLOCAL, 2);
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#endif
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#ifdef CPU_NLM
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MIPS_RW32_COP0_SEL(pagegrain, MIPS_COP_0_TLB_PG_MASK, 1);
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#endif
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#if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */
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MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
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MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
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#endif
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MIPS_RW32_COP0(prid, MIPS_COP_0_PRID);
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/* XXX 64-bit? */
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MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1);
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#if defined(CPU_MIPS24K) || defined(CPU_MIPS34K) || \
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defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) || \
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defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) || \
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defined(CPU_PROAPTIV)
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/* MIPS32/64 r2 intctl */
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MIPS_RW32_COP0_SEL(intctl, MIPS_COP_0_INTCTL, 1);
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#endif
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#ifdef CPU_XBURST
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MIPS_RW32_COP0_SEL(xburst_mbox0, MIPS_COP_0_XBURST_MBOX, 0);
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MIPS_RW32_COP0_SEL(xburst_mbox1, MIPS_COP_0_XBURST_MBOX, 1);
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MIPS_RW32_COP0_SEL(xburst_core_ctl, MIPS_COP_0_XBURST_C12, 2);
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MIPS_RW32_COP0_SEL(xburst_core_sts, MIPS_COP_0_XBURST_C12, 3);
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MIPS_RW32_COP0_SEL(xburst_reim, MIPS_COP_0_XBURST_C12, 4);
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#endif
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MIPS_RW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
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MIPS_RW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1);
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MIPS_RW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2);
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MIPS_RW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3);
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MIPS_RW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
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MIPS_RW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1);
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MIPS_RW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2);
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MIPS_RW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3);
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MIPS_RW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0);
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MIPS_RW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1);
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MIPS_RW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2);
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MIPS_RW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3);
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MIPS_RW32_COP0(hwrena, MIPS_COP_0_HWRENA);
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#undef MIPS_RW32_COP0
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#undef MIPS_RW32_COP0_SEL
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static __inline register_t
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intr_disable(void)
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{
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register_t s;
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s = mips_rd_status();
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mips_wr_status(s & ~MIPS_SR_INT_IE);
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return (s & MIPS_SR_INT_IE);
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}
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static __inline register_t
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intr_enable(void)
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{
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register_t s;
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s = mips_rd_status();
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mips_wr_status(s | MIPS_SR_INT_IE);
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return (s);
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}
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static __inline void
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intr_restore(register_t ie)
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{
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if (ie == MIPS_SR_INT_IE) {
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intr_enable();
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}
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}
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static __inline uint32_t
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set_intr_mask(uint32_t mask)
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{
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uint32_t ostatus;
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ostatus = mips_rd_status();
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mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK);
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mips_wr_status(mask);
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return (ostatus);
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}
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static __inline uint32_t
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get_intr_mask(void)
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{
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return (mips_rd_status() & MIPS_SR_INT_MASK);
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}
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static __inline void
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breakpoint(void)
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{
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__asm __volatile ("break");
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}
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#if defined(__GNUC__) && !defined(__mips_o32)
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#define mips3_ld(a) (*(const volatile uint64_t *)(a))
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#define mips3_sd(a, v) (*(volatile uint64_t *)(a) = (v))
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#else
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uint64_t mips3_ld(volatile uint64_t *va);
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void mips3_sd(volatile uint64_t *, uint64_t);
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#endif /* __GNUC__ */
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#endif /* _KERNEL */
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#define readb(va) (*(volatile uint8_t *) (va))
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#define readw(va) (*(volatile uint16_t *) (va))
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#define readl(va) (*(volatile uint32_t *) (va))
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#if defined(__GNUC__) && !defined(__mips_o32)
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#define readq(a) (*(volatile uint64_t *)(a))
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#endif
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#define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
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#define writew(va, d) (*(volatile uint16_t *) (va) = (d))
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#define writel(va, d) (*(volatile uint32_t *) (va) = (d))
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#if defined(__GNUC__) && !defined(__mips_o32)
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#define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
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#endif
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#endif /* !_MACHINE_CPUFUNC_H_ */
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