9a8f61fb5b
X1000 systems on chips. Imgtec CI20 and Ingenic CANNA boards supported. Submitted by: Alexander Kabaev <kan@FreeBSD.org> Reviewed by: Ruslan Bukin <br@FreeBSD.org> Sponsored by: DARPA, AFRL
74 lines
3.0 KiB
C
74 lines
3.0 KiB
C
/*-
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* Copyright (c) 2015 Alexander Kabaev <kan@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef JZ4780_CPUREGS_H
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#define JZ4780_CPUREGS_H
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/* Core control register */
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#define JZ_CORECTL_SLP1M_SHIFT 17
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#define JZ_CORECTL_SLP1M (1u << JZ_CORECTL_SLP1M_SHIFT)
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#define JZ_CORECTL_SLP0M_SHIFT 16
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#define JZ_CORECTL_SLP0M (1u << JZ_CORECTL_SLP0M_SHIFT)
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#define JZ_CORECTL_RPC1_SHIFT 9
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#define JZ_CORECTL_RPC1 (1u << JZ_CORECTL_RPC1_SHIFT)
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#define JZ_CORECTL_RPC0_SHIFT 8
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#define JZ_CORECTL_RPC0 (1u << JZ_CORECTL_RPC0_SHIFT)
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#define JZ_CORECTL_SWRST1_SHIFT 1
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#define JZ_CORECTL_SWRST1 (1u << JZ_CORECTL_SWRST1_SHIFT)
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#define JZ_CORECTL_SWRST0_SHIFT 0
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#define JZ_CORECTL_SWRST0 (1u << JZ_CORECTL_SWRST0_SHIFT)
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/* Core status register */
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#define JZ_CORESTS_SLP1_SHIFT 17
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#define JZ_CORESTS_SLP1 (1u << JZ_CORESTS_SLP1_SHIFT)
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#define JZ_CORESTS_SLP0_SHIFT 16
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#define JZ_CORESTS_SLP0 (1u << JZ_CORESTS_SLP0_SHIFT)
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#define JZ_CORESTS_IRQ1P_SHIFT 9
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#define JZ_CORESTS_IRQ1P (1u << JZ_CORESTS_IRQ1P_SHIFT)
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#define JZ_CORESTS_IRQ0P_SHIFT 8
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#define JZ_CORESTS_IRQ0P (1u << JZ_CORESTS_IRQ0P_SHIFT)
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#define JZ_CORESTS_MIRQ1P_SHIFT 1
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#define JZ_CORESTS_MIRQ1P (1u << JZ_CORESTS_MIRQ1P_SHIFT)
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#define JZ_CORESTS_MIRQ0P_SHIFT 0
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#define JZ_CORESTS_MIRQ0P (1u << JZ_CORESTS_MIRQ0P_SHIFT)
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/* Reset entry and IRQ mask */
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#define JZ_REIM_ENTRY_SHIFT 16
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#define JZ_REIM_ENTRY_WIDTH 16
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#define JZ_REIM_ENTRY_MASK (0xFFFFu << JZ_REIM_ENTRY_SHIFT)
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#define JZ_REIM_IRQ1M_SHIFT 9
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#define JZ_REIM_IRQ1M (1u << JZ_REIM_IRQ1M_SHIFT)
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#define JZ_REIM_IRQ0M_SHIFT 8
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#define JZ_REIM_IRQ0M (1u << JZ_REIM_IRQ0M_SHIFT)
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#define JZ_REIM_MIRQ1M_SHIFT 1
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#define JZ_REIM_MIRQ1M (1u << JZ_REIM_MIRQ1M_SHIFT)
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#define JZ_REIM_MIRQ0M_SHIFT 0
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#define JZ_REIM_MIRQ0M (1u << JZ_REIM_MIRQ0M_SHIFT)
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#endif /* JZ4780_CPUREGS_H */
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