5d9b71c225
Linux ath9k. The ath9k ar9002_hw_init_cal() isn't entirely clear about what is supposed to be called for what chipsets, so I'm ignoring the rest of it and just porting the AR9285 init cal path as-is and leaving the rest alone. Subsequent commits may also tidy up the Merlin (AR9285) and other chipset support. Obtained from: Linux ath9k
131 lines
5.3 KiB
C
131 lines
5.3 KiB
C
/*
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* Copyright (c) 2008-2010 Atheros Communications Inc.
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* Copyright (c) 2010-2011 Adrian Chadd, Xenion Pty Ltd.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __ATH_AR9285PHY_H__
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#define __ATH_AR9285PHY_H__
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#define AR9285_AN_RF2G1 0x7820
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#define AR9285_AN_RF2G1_ENPACAL 0x00000800
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#define AR9285_AN_RF2G1_ENPACAL_S 11
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#define AR9285_AN_RF2G1_PDPADRV1 0x02000000
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#define AR9285_AN_RF2G1_PDPADRV1_S 25
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#define AR9285_AN_RF2G1_PDPADRV2 0x01000000
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#define AR9285_AN_RF2G1_PDPADRV2_S 24
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#define AR9285_AN_RF2G1_PDPAOUT 0x00800000
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#define AR9285_AN_RF2G1_PDPAOUT_S 23
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#define AR9285_AN_RF2G2 0x7824
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#define AR9285_AN_RF2G2_OFFCAL 0x00001000
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#define AR9285_AN_RF2G2_OFFCAL_S 12
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#define AR9285_AN_RF2G3 0x7828
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#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
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#define AR9285_AN_RF2G3_PDVCCOMP_S 25
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#define AR9285_AN_RF2G3_OB_0 0x00E00000
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#define AR9285_AN_RF2G3_OB_0_S 21
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#define AR9285_AN_RF2G3_OB_1 0x001C0000
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#define AR9285_AN_RF2G3_OB_1_S 18
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#define AR9285_AN_RF2G3_OB_2 0x00038000
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#define AR9285_AN_RF2G3_OB_2_S 15
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#define AR9285_AN_RF2G3_OB_3 0x00007000
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#define AR9285_AN_RF2G3_OB_3_S 12
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#define AR9285_AN_RF2G3_OB_4 0x00000E00
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#define AR9285_AN_RF2G3_OB_4_S 9
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#define AR9285_AN_RF2G3_DB1_0 0x000001C0
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#define AR9285_AN_RF2G3_DB1_0_S 6
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#define AR9285_AN_RF2G3_DB1_1 0x00000038
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#define AR9285_AN_RF2G3_DB1_1_S 3
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#define AR9285_AN_RF2G3_DB1_2 0x00000007
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#define AR9285_AN_RF2G3_DB1_2_S 0
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#define AR9285_AN_RF2G4 0x782C
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#define AR9285_AN_RF2G4_DB1_3 0xE0000000
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#define AR9285_AN_RF2G4_DB1_3_S 29
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#define AR9285_AN_RF2G4_DB1_4 0x1C000000
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#define AR9285_AN_RF2G4_DB1_4_S 26
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#define AR9285_AN_RF2G4_DB2_0 0x03800000
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#define AR9285_AN_RF2G4_DB2_0_S 23
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#define AR9285_AN_RF2G4_DB2_1 0x00700000
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#define AR9285_AN_RF2G4_DB2_1_S 20
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#define AR9285_AN_RF2G4_DB2_2 0x000E0000
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#define AR9285_AN_RF2G4_DB2_2_S 17
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#define AR9285_AN_RF2G4_DB2_3 0x0001C000
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#define AR9285_AN_RF2G4_DB2_3_S 14
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#define AR9285_AN_RF2G4_DB2_4 0x00003800
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#define AR9285_AN_RF2G4_DB2_4_S 11
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#define AR9285_RF2G5 0x7830
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#define AR9285_RF2G5_IC50TX 0xfffff8ff
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#define AR9285_RF2G5_IC50TX_SET 0x00000400
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#define AR9285_RF2G5_IC50TX_XE_SET 0x00000500
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#define AR9285_RF2G5_IC50TX_CLEAR 0x00000700
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#define AR9285_RF2G5_IC50TX_CLEAR_S 8
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#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000
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#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
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#define AR_PHY_TX_GAIN_CLC 0x0000001E
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#define AR_PHY_TX_GAIN_CLC_S 1
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#define AR_PHY_TX_GAIN 0x0007F000
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#define AR_PHY_TX_GAIN_S 12
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#define AR_PHY_CLC_TBL1 0xa35c
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#define AR_PHY_CLC_I0 0x07ff0000
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#define AR_PHY_CLC_I0_S 16
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#define AR_PHY_CLC_Q0 0x0000ffd0
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#define AR_PHY_CLC_Q0_S 5
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#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
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#define AR_PHY_9285_FAST_DIV_BIAS 0x00007E00
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#define AR_PHY_9285_FAST_DIV_BIAS_S 9
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#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
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#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
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#define AR_PHY_9285_ANT_DIV_CTL_S 24
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#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
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#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
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#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
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#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
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#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
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#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
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#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
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#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
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#define AR_PHY_9285_ANT_DIV_LNA1 2
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#define AR_PHY_9285_ANT_DIV_LNA2 1
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#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
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#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
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#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
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#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
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/* for AR_PHY_CCK_DETECT */
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#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
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#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
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#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
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#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
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#endif
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