127 lines
5.3 KiB
C
127 lines
5.3 KiB
C
/* $NetBSD: s3c2xx0reg.h,v 1.4 2004/02/12 03:47:29 bsh Exp $ */
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/*-
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* Copyright (c) 2002, 2003 Fujitsu Component Limited
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* Copyright (c) 2002, 2003 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The Fujitsu Component Limited nor the name of
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* Genetec corporation may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
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* CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
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* CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* s3c2410-specific registers */
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#define UMCON_AFC (1 << 4) /* auto flow control */
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#define UMSTAT_DCTS (1 << 2) /* CTS change */
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#define ULCON_IR (1 << 6)
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#define ULCON_PARITY_SHIFT 3
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/*
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* Exynos-specific
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*
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* UFSTAT_TXFULL register differs between Exynos and others.
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* Others have UFSTAT_TXFULL (1 << 9)
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*/
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#define UFSTAT_TXFULL (1 << 24)
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#define SSCOM_UINTM 0x038
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#define SSCOM_UINTP 0x030
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/* common for s3c2800 and s3c24x0 */
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#define SSCOM_ULCON 0x00 /* UART line control */
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#define ULCON_PARITY_NONE (0 << ULCON_PARITY_SHIFT)
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#define ULCON_PARITY_ODD (4 << ULCON_PARITY_SHIFT)
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#define ULCON_PARITY_EVEN (5 << ULCON_PARITY_SHIFT)
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#define ULCON_PARITY_ONE (6 << ULCON_PARITY_SHIFT)
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#define ULCON_PARITY_ZERO (7 << ULCON_PARITY_SHIFT)
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#define ULCON_STOP (1 << 2)
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#define ULCON_LENGTH_5 0
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#define ULCON_LENGTH_6 1
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#define ULCON_LENGTH_7 2
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#define ULCON_LENGTH_8 3
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#define SSCOM_UCON 0x04 /* UART control */
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#define UCON_TXINT_TYPE (1 << 9) /* Tx interrupt. 0=pulse,1=level */
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#define UCON_TXINT_TYPE_LEVEL UCON_TXINT_TYPE
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#define UCON_TXINT_TYPE_PULSE 0
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#define UCON_RXINT_TYPE (1 << 8) /* Rx interrupt */
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#define UCON_RXINT_TYPE_LEVEL UCON_RXINT_TYPE
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#define UCON_RXINT_TYPE_PULSE 0
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#define UCON_TOINT (1 << 7) /* Rx timeout interrupt */
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#define UCON_ERRINT (1 << 6) /* receive error interrupt */
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#define UCON_LOOP (1 << 5) /* loopback */
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#define UCON_SBREAK (1 << 4) /* send break */
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#define UCON_TXMODE_DISABLE (0 << 2)
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#define UCON_TXMODE_INT (1 << 2)
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#define UCON_TXMODE_DMA (2 << 2)
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#define UCON_TXMODE_MASK (3 << 2)
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#define UCON_RXMODE_DISABLE (0 << 0)
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#define UCON_RXMODE_INT (1 << 0)
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#define UCON_RXMODE_DMA (2 << 0)
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#define UCON_RXMODE_MASK (3 << 0)
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#define SSCOM_UFCON 0x08 /* FIFO control */
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#define UFCON_TXTRIGGER_0 (0 << 6)
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#define UFCON_TXTRIGGER_4 (1 << 6)
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#define UFCON_TXTRIGGER_8 (2 << 6)
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#define UFCON_TXTRIGGER_16 (3 << 6)
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#define UFCON_RXTRIGGER_4 (0 << 4)
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#define UFCON_RXTRIGGER_8 (1 << 4)
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#define UFCON_RXTRIGGER_12 (2 << 4)
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#define UFCON_RXTRIGGER_16 (3 << 4)
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#define UFCON_TXFIFO_RESET (1 << 2)
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#define UFCON_RXFIFO_RESET (1 << 1)
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#define UFCON_FIFO_ENABLE (1 << 0)
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#define SSCOM_UMCON 0x0c /* MODEM control */
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#define UMCON_RTS (1 << 0) /* Request to send */
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#define SSCOM_UTRSTAT 0x10 /* Status register */
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#define UTRSTAT_TXSHIFTER_EMPTY ( 1<< 2)
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#define UTRSTAT_TXEMPTY (1 << 1) /* TX fifo or buffer empty */
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#define UTRSTAT_RXREADY (1 << 0) /* RX fifo or buffer is not empty */
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#define SSCOM_UERSTAT 0x14 /* Error status register */
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#define UERSTAT_BREAK (1 << 3) /* Break signal, not 2410 */
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#define UERSTAT_FRAME (1 << 2) /* Frame error */
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#define UERSTAT_PARITY (1 << 1) /* Parity error, not 2410 */
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#define UERSTAT_OVERRUN (1 << 0) /* Overrun */
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#define UERSTAT_ALL_ERRORS \
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(UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY)
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#define SSCOM_UFSTAT 0x18 /* Fifo status register */
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#define UFSTAT_RXFULL (1 <<8) /* Rx fifo full */
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#define UFSTAT_TXCOUNT_SHIFT 4 /* TX FIFO count */
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#define UFSTAT_TXCOUNT (0x0f << UFSTAT_TXCOUNT_SHIFT)
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#define UFSTAT_RXCOUNT_SHIFT 0 /* RX FIFO count */
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#define UFSTAT_RXCOUNT (0x0f << UFSTAT_RXCOUNT_SHIFT)
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#define SSCOM_UMSTAT 0x1c /* Modem status register */
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#define UMSTAT_CTS (1 << 0) /* Clear to send */
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#if _BYTE_ORDER == _LITTLE_ENDIAN
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#define SSCOM_UTXH 0x20 /* Transmit data register */
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#define SSCOM_URXH 0x24 /* Receive data register */
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#else
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#define SSCOM_UTXH 0x23 /* Transmit data register */
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#define SSCOM_URXH 0x27 /* Receive data register */
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#endif
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#define SSCOM_UBRDIV 0x28 /* baud-reate divisor */
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#define SSCOM_SIZE 0x2c
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