66cc5279f5
Linux ath9k only enables this for AR9280 and later NICs; so create a capability for it so it isn't enabled for earlier NICs. Enabling hardware PS-POLL support will come in a later commit and will be disabled by default.
435 lines
13 KiB
C
435 lines
13 KiB
C
/*
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* Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_devid.h"
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#include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */
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#include "ar9002/ar9280.h"
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#include "ar9002/ar9285.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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#include "ar9002/ar9285.ini"
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#include "ar9002/ar9285v2.ini"
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#include "ar9002/ar9280v2.ini" /* XXX ini for tx/rx gain */
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#include "ar9002/ar9285_cal.h"
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static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
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.calName = "IQ", .calType = IQ_MISMATCH_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = PER_MAX_LOG_COUNT,
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.calCollect = ar5416IQCalCollect,
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.calPostProc = ar5416IQCalibration
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};
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static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
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.calName = "ADC Gain", .calType = ADC_GAIN_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = PER_MIN_LOG_COUNT,
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.calCollect = ar5416AdcGainCalCollect,
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.calPostProc = ar5416AdcGainCalibration
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};
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static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
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.calName = "ADC DC", .calType = ADC_DC_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = PER_MIN_LOG_COUNT,
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.calCollect = ar5416AdcDcCalCollect,
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.calPostProc = ar5416AdcDcCalibration
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};
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static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
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.calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = INIT_LOG_COUNT,
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.calCollect = ar5416AdcDcCalCollect,
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.calPostProc = ar5416AdcDcCalibration
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};
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static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
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static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
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static void ar9285WriteIni(struct ath_hal *ah,
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const struct ieee80211_channel *chan);
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static void
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ar9285AniSetup(struct ath_hal *ah)
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{
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/* NB: disable ANI for reliable RIFS rx */
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ar5416AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE);
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}
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/*
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* Attach for an AR9285 part.
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*/
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static struct ath_hal *
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ar9285Attach(uint16_t devid, HAL_SOFTC sc,
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HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
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HAL_STATUS *status)
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{
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struct ath_hal_9285 *ahp9285;
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struct ath_hal_5212 *ahp;
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struct ath_hal *ah;
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uint32_t val;
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HAL_STATUS ecode;
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HAL_BOOL rfStatus;
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HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
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__func__, sc, (void*) st, (void*) sh);
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/* NB: memory is returned zero'd */
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ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
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if (ahp9285 == AH_NULL) {
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HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
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"%s: cannot allocate memory for state block\n", __func__);
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*status = HAL_ENOMEM;
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return AH_NULL;
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}
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ahp = AH5212(ahp9285);
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ah = &ahp->ah_priv.h;
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ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
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/* XXX override with 9285 specific state */
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/* override 5416 methods for our needs */
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ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
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ah->ah_configPCIE = ar9285ConfigPCIE;
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ah->ah_setTxPower = ar9285SetTransmitPower;
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ah->ah_setBoardValues = ar9285SetBoardValues;
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AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
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AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
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AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
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AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
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AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
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if (AR_SREV_KITE_12_OR_LATER(ah))
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AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware;
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AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal;
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AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
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AH5416(ah)->ah_writeIni = ar9285WriteIni;
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AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
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AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
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ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1;
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if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
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/* reset chip */
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
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__func__);
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ecode = HAL_EIO;
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goto bad;
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}
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if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
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__func__);
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ecode = HAL_EIO;
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goto bad;
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}
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/* Read Revisions from Chips before taking out of reset */
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val = OS_REG_READ(ah, AR_SREV);
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HALDEBUG(ah, HAL_DEBUG_ATTACH,
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"%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
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__func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
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MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
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/* NB: include chip type to differentiate from pre-Sowl versions */
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AH_PRIVATE(ah)->ah_macVersion =
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(val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
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AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
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AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
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/* setup common ini data; rf backends handle remainder */
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if (AR_SREV_KITE_12_OR_LATER(ah)) {
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HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
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HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
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HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
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ar9285PciePhy_clkreq_always_on_L1_v2, 2);
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} else {
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HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
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HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
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HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
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ar9285PciePhy_clkreq_always_on_L1, 2);
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}
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ar5416AttachPCIE(ah);
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ecode = ath_hal_v4kEepromAttach(ah);
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if (ecode != HAL_OK)
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goto bad;
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if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
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__func__);
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ecode = HAL_EIO;
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goto bad;
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}
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AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
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if (!ar5212ChipTest(ah)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
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__func__);
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ecode = HAL_ESELFTEST;
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goto bad;
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}
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/*
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* Set correct Baseband to analog shift
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* setting to access analog chips.
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*/
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OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
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/* Read Radio Chip Rev Extract */
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AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
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switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
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case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
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case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
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break;
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default:
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if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
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AH_PRIVATE(ah)->ah_analog5GhzRev =
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AR_RAD5133_SREV_MAJOR;
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break;
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}
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#ifdef AH_DEBUG
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: 5G Radio Chip Rev 0x%02X is not supported by "
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"this driver\n", __func__,
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AH_PRIVATE(ah)->ah_analog5GhzRev);
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ecode = HAL_ENOTSUPP;
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goto bad;
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#endif
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}
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rfStatus = ar9285RfAttach(ah, &ecode);
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if (!rfStatus) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
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__func__, ecode);
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goto bad;
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}
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HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
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6);
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if (AR_SREV_9285E_20(ah))
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ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n");
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/* setup txgain table */
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switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
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case AR5416_EEP_TXGAIN_HIGH_POWER:
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if (AR_SREV_9285E_20(ah))
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HAL_INI_INIT(&ahp9285->ah_ini_txgain,
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ar9285Modes_XE2_0_high_power, 6);
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else
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HAL_INI_INIT(&ahp9285->ah_ini_txgain,
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ar9285Modes_high_power_tx_gain_v2, 6);
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break;
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case AR5416_EEP_TXGAIN_ORIG:
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if (AR_SREV_9285E_20(ah))
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HAL_INI_INIT(&ahp9285->ah_ini_txgain,
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ar9285Modes_XE2_0_normal_power, 6);
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else
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HAL_INI_INIT(&ahp9285->ah_ini_txgain,
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ar9285Modes_original_tx_gain_v2, 6);
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break;
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default:
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HALASSERT(AH_FALSE);
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goto bad; /* XXX ? try to continue */
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}
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/*
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* Got everything we need now to setup the capabilities.
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*/
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if (!ar9285FillCapabilityInfo(ah)) {
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ecode = HAL_EEREAD;
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goto bad;
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}
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/* Disable 11n for the AR2427 */
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if (devid == AR2427_DEVID_PCIE)
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AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE;
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ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
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if (ecode != HAL_OK) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: error getting mac address from EEPROM\n", __func__);
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goto bad;
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}
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/* XXX How about the serial number ? */
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/* Read Reg Domain */
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AH_PRIVATE(ah)->ah_currentRD =
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ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
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/*
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* ah_miscMode is populated by ar5416FillCapabilityInfo()
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* starting from griffin. Set here to make sure that
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* AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
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* placed into hardware.
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*/
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if (ahp->ah_miscMode != 0)
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OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
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ar9285AniSetup(ah); /* Anti Noise Immunity */
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/* Setup noise floor min/max/nominal values */
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AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
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AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
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AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
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/* XXX no 5ghz values? */
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ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
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HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
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return ah;
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bad:
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if (ah != AH_NULL)
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ah->ah_detach(ah);
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if (status)
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*status = ecode;
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return AH_NULL;
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}
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static void
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ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
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{
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if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
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ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
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OS_DELAY(1000);
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OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
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OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
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}
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}
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static void
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ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
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{
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u_int modesIndex, freqIndex;
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int regWrites = 0;
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/* Setup the indices for the next set of register array writes */
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/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
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freqIndex = 2;
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if (IEEE80211_IS_CHAN_HT40(chan))
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modesIndex = 3;
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else if (IEEE80211_IS_CHAN_108G(chan))
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modesIndex = 5;
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else
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modesIndex = 4;
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/* Set correct Baseband to analog shift setting to access analog chips. */
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OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
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OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
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regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
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modesIndex, regWrites);
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if (AR_SREV_KITE_12_OR_LATER(ah)) {
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regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
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modesIndex, regWrites);
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}
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regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
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1, regWrites);
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}
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/*
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* Fill all software cached or static hardware state information.
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* Return failure if capabilities are to come from EEPROM and
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* cannot be read.
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*/
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static HAL_BOOL
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ar9285FillCapabilityInfo(struct ath_hal *ah)
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{
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HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
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if (!ar5416FillCapabilityInfo(ah))
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return AH_FALSE;
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pCap->halNumGpioPins = 12;
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pCap->halWowSupport = AH_TRUE;
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pCap->halWowMatchPatternExact = AH_TRUE;
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#if 0
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pCap->halWowMatchPatternDword = AH_TRUE;
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#endif
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/* AR9285 has 2 antennas but is a 1x1 stream device */
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pCap->halTxStreams = 1;
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pCap->halRxStreams = 1;
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pCap->halCSTSupport = AH_TRUE;
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pCap->halRifsRxSupport = AH_TRUE;
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pCap->halRifsTxSupport = AH_TRUE;
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pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
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pCap->halExtChanDfsSupport = AH_TRUE;
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#if 0
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/* XXX bluetooth */
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pCap->halBtCoexSupport = AH_TRUE;
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#endif
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pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
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pCap->hal4kbSplitTransSupport = AH_FALSE;
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if (AR_SREV_KITE_12_OR_LATER(ah))
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pCap->halHasPsPollSupport = AH_TRUE;
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pCap->halRxStbcSupport = 1;
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pCap->halTxStbcSupport = 1;
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return AH_TRUE;
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}
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HAL_BOOL
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ar9285SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
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{
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#define ANTENNA0_CHAINMASK 0x1
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#define ANTENNA1_CHAINMASK 0x2
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struct ath_hal_5416 *ahp = AH5416(ah);
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/* Antenna selection is done by setting the tx/rx chainmasks approp. */
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switch (settings) {
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case HAL_ANT_FIXED_A:
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/* Enable first antenna only */
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ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK;
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ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK;
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break;
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case HAL_ANT_FIXED_B:
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/* Enable second antenna only, after checking capability */
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if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK)
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ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK;
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ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK;
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break;
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case HAL_ANT_VARIABLE:
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/* Restore original chainmask settings */
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/* XXX */
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ahp->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
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ahp->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
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break;
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}
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return AH_TRUE;
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#undef ANTENNA0_CHAINMASK
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#undef ANTENNA1_CHAINMASK
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}
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static const char*
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ar9285Probe(uint16_t vendorid, uint16_t devid)
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{
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if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE)
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return "Atheros 9285";
|
|
if (vendorid == ATHEROS_VENDOR_ID && (devid == AR2427_DEVID_PCIE))
|
|
return "Atheros 2427";
|
|
|
|
return AH_NULL;
|
|
}
|
|
AH_CHIP(AR9285, ar9285Probe, ar9285Attach);
|