1b40801722
status register rather than 0. Without this, a single hardware volume event triggers an interrupt storm. - Implement hardware volume control for the Maestro chips. This version only handles the case where both channels are adjusted at the same time. Reviewed by: cg
350 lines
9.9 KiB
C
350 lines
9.9 KiB
C
/*-
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* Copyright (c) 1999-2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: maestro_reg.h,v 1.10 2000/08/29 17:27:29 taku Exp $
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* $FreeBSD$
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*/
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#ifndef MAESTRO_REG_H_INCLUDED
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#define MAESTRO_REG_H_INCLUDED
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/* -----------------------------
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* PCI config registers
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*/
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/* Legacy emulation */
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#define CONF_LEGACY 0x40
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#define LEGACY_DISABLED 0x8000
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/* Chip configurations */
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#define CONF_MAESTRO 0x50
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#define MAESTRO_CHIBUS 0x00100000
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#define MAESTRO_POSTEDWRITE 0x00000080
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#define MAESTRO_DMA_PCITIMING 0x00000040
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#define MAESTRO_SWAP_LR 0x00000010
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/* ACPI configurations */
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#define CONF_ACPI_STOPCLOCK 0x54
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#define ACPI_PART_2ndC_CLOCK 15
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#define ACPI_PART_CODEC_CLOCK 14
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#define ACPI_PART_978 13 /* Docking station or something */
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#define ACPI_PART_SPDIF 12
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#define ACPI_PART_GLUE 11 /* What? */
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#define ACPI_PART_DAA 10
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#define ACPI_PART_PCI_IF 9
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#define ACPI_PART_HW_VOL 8
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#define ACPI_PART_GPIO 7
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#define ACPI_PART_ASSP 6
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#define ACPI_PART_SB 5
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#define ACPI_PART_FM 4
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#define ACPI_PART_RINGBUS 3
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#define ACPI_PART_MIDI 2
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#define ACPI_PART_GAME_PORT 1
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#define ACPI_PART_WP 0
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/* Power management */
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#define CONF_PM_PTR 0x34 /* BYTE R */
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#define PM_CID 0 /* BYTE R */
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#define PPMI_CID 1
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#define PM_CTRL 4 /* BYTE RW */
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#define PPMI_D0 0 /* Full power */
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#define PPMI_D1 1 /* Medium power */
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#define PPMI_D2 2 /* Low power */
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#define PPMI_D3 3 /* Turned off */
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/* -----------------------------
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* I/O ports
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*/
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/* Direct Sound Processor (aka WP) */
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#define PORT_DSP_DATA 0x00 /* WORD RW */
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#define PORT_DSP_INDEX 0x02 /* WORD RW */
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#define PORT_INT_STAT 0x04 /* WORD RW */
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#define PORT_SAMPLE_CNT 0x06 /* WORD RO */
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/* WaveCache */
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#define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */
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#define PORT_WAVCACHE_DATA 0x12 /* WORD RW */
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#define WAVCACHE_PCMBAR 0x1fc
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#define WAVCACHE_WTBAR 0x1f0
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#define WAVCACHE_BASEADDR_SHIFT 12
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#define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8
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#define WAVCACHE_CHCTL_U8 0x0004
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#define WAVCACHE_CHCTL_STEREO 0x0002
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#define WAVCACHE_CHCTL_DECREMENTAL 0x0001
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#define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */
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#define WAVCACHE_EXTRA_CH_ENABLED 0x0200
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#define WAVCACHE_ENABLED 0x0100
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#define WAVCACHE_CH_60_ENABLED 0x0080
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#define WAVCACHE_WTSIZE_MASK 0x0060
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#define WAVCACHE_WTSIZE_1MB 0x0000
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#define WAVCACHE_WTSIZE_2MB 0x0020
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#define WAVCACHE_WTSIZE_4MB 0x0040
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#define WAVCACHE_WTSIZE_8MB 0x0060
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#define WAVCACHE_SGC_MASK 0x000c
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#define WAVCACHE_SGC_DISABLED 0x0000
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#define WAVCACHE_SGC_40_47 0x0004
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#define WAVCACHE_SGC_32_47 0x0008
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#define WAVCACHE_TESTMODE 0x0001
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/* Host Interruption */
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#define PORT_HOSTINT_CTRL 0x18 /* WORD RW */
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#define HOSTINT_CTRL_SOFT_RESET 0x8000
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#define HOSTINT_CTRL_DSOUND_RESET 0x4000
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#define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400
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#define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100
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#define HOSTINT_CTRL_HWVOL_ENABLED 0x0040
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#define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010
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#define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008
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#define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004
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#define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002
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#define HOSTINT_CTRL_SB_INT_ENABLED 0x0001
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#define PORT_HOSTINT_STAT 0x1a /* BYTE RW */
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#define HOSTINT_STAT_HWVOL 0x40
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#define HOSTINT_STAT_ASSP 0x10
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#define HOSTINT_STAT_ISDN 0x08
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#define HOSTINT_STAT_DSOUND 0x04
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#define HOSTINT_STAT_MPU401 0x02
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#define HOSTINT_STAT_SB 0x01
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/* Hardware volume */
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#define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */
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#define PORT_HWVOL_VOICE 0x1d /* BYTE RW */
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#define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */
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#define PORT_HWVOL_MASTER 0x1f /* BYTE RW */
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#define HWVOL_NOP 0x88
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#define HWVOL_MUTE 0x99
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#define HWVOL_UP 0xaa
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#define HWVOL_DOWN 0x66
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/* CODEC */
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#define PORT_CODEC_CMD 0x30 /* BYTE W */
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#define CODEC_CMD_READ 0x80
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#define CODEC_CMD_WRITE 0x00
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#define CODEC_CMD_ADDR_MASK 0x7f
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#define PORT_CODEC_STAT 0x30 /* BYTE R */
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#define CODEC_STAT_MASK 0x01
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#define CODEC_STAT_RW_DONE 0x00
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#define CODEC_STAT_PROGLESS 0x01
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#define PORT_CODEC_REG 0x32 /* WORD RW */
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/* Ring bus control */
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#define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */
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#define RINGBUS_CTRL_I2S_ENABLED 0x80000000
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#define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000
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#define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000
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#define RINGBUS_CTRL_AC97_SWRESET 0x08000000
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#define RINGBUS_CTRL_IODMA_PLAYBACK_ENABLED 0x04000000
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#define RINGBUS_CTRL_IODMA_RECORD_ENABLED 0x02000000
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#define RINGBUS_SRC_MIC 20
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#define RINGBUS_SRC_I2S 16
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#define RINGBUS_SRC_ADC 12
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#define RINGBUS_SRC_MODEM 8
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#define RINGBUS_SRC_DSOUND 4
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#define RINGBUS_SRC_ASSP 0
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#define RINGBUS_DEST_MONORAL 000
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#define RINGBUS_DEST_STEREO 010
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#define RINGBUS_DEST_NONE 0
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#define RINGBUS_DEST_DAC 1
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#define RINGBUS_DEST_MODEM_IN 2
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#define RINGBUS_DEST_RESERVED3 3
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#define RINGBUS_DEST_DSOUND_IN 4
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#define RINGBUS_DEST_ASSP_IN 5
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/* General Purpose I/O */
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#define PORT_GPIO_DATA 0x60 /* WORD RW */
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#define PORT_GPIO_MASK 0x64 /* WORD RW */
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#define PORT_GPIO_DIR 0x68 /* WORD RW */
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/* Application Specific Signal Processor */
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#define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */
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#define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */
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#define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */
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#define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */
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#define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */
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#define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */
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#define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */
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#define PORT_ASSP_INT_STAT 0xac /* BYTE RW */
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/* -----------------------------
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* Wave Processor Indexed Data Registers.
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*/
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#define WPREG_DATA_PORT 0
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#define WPREG_CRAM_PTR 1
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#define WPREG_CRAM_DATA 2
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#define WPREG_WAVE_DATA 3
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#define WPREG_WAVE_PTR_LOW 4
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#define WPREG_WAVE_PTR_HIGH 5
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#define WPREG_TIMER_FREQ 6
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#define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */
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#define WP_TIMER_FREQ_PRESCALE_SHIFT 5
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#define WP_TIMER_FREQ_DIVIDE_MASK 0x001f
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#define WP_TIMER_FREQ_DIVIDE_SHIFT 0
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#define WPREG_WAVE_ROMRAM 7
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#define WP_WAVE_VIRTUAL_ENABLED 0x0400
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#define WP_WAVE_8BITRAM_ENABLED 0x0200
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#define WP_WAVE_DRAM_ENABLED 0x0100
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#define WP_WAVE_RAMSPLIT_MASK 0x00ff
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#define WP_WAVE_RAMSPLIT_SHIFT 0
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#define WPREG_BASE 12
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#define WP_PARAOUT_BASE_MASK 0xf000
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#define WP_PARAOUT_BASE_SHIFT 12
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#define WP_PARAIN_BASE_MASK 0x0f00
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#define WP_PARAIN_BASE_SHIFT 8
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#define WP_SERIAL0_BASE_MASK 0x00f0
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#define WP_SERIAL0_BASE_SHIFT 4
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#define WP_SERIAL1_BASE_MASK 0x000f
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#define WP_SERIAL1_BASE_SHIFT 0
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#define WPREG_TIMER_ENABLE 17
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#define WPREG_TIMER_START 23
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/* -----------------------------
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* Audio Processing Unit.
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*/
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#define APUREG_APUTYPE 0
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#define APU_DMA_ENABLED 0x4000
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#define APU_INT_ON_LOOP 0x2000
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#define APU_ENDCURVE 0x1000
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#define APU_APUTYPE_MASK 0x00f0
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#define APU_FILTERTYPE_MASK 0x000c
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#define APU_FILTERQ_MASK 0x0003
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/* APU types */
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#define APU_APUTYPE_SHIFT 4
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#define APUTYPE_INACTIVE 0
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#define APUTYPE_16BITLINEAR 1
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#define APUTYPE_16BITSTEREO 2
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#define APUTYPE_8BITLINEAR 3
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#define APUTYPE_8BITSTEREO 4
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#define APUTYPE_8BITDIFF 5
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#define APUTYPE_DIGITALDELAY 6
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#define APUTYPE_DUALTAP_READER 7
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#define APUTYPE_CORRELATOR 8
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#define APUTYPE_INPUTMIXER 9
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#define APUTYPE_WAVETABLE 10
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#define APUTYPE_RATECONV 11
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#define APUTYPE_16BITPINGPONG 12
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/* APU type 13 through 15 are reserved. */
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/* Filter types */
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#define APU_FILTERTYPE_SHIFT 2
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#define FILTERTYPE_2POLE_LOPASS 0
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#define FILTERTYPE_2POLE_BANDPASS 1
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#define FILTERTYPE_2POLE_HIPASS 2
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#define FILTERTYPE_1POLE_LOPASS 3
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#define FILTERTYPE_1POLE_HIPASS 4
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#define FILTERTYPE_PASSTHROUGH 5
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/* Filter Q */
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#define APU_FILTERQ_SHIFT 0
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#define FILTERQ_LESSQ 0
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#define FILTERQ_MOREQ 3
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/* APU register 2 */
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#define APUREG_FREQ_LOBYTE 2
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#define APU_FREQ_LOBYTE_MASK 0xff00
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#define APU_plus6dB 0x0010
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/* APU register 3 */
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#define APUREG_FREQ_HIWORD 3
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#define APU_FREQ_HIWORD_MASK 0x0fff
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/* Frequency */
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#define APU_FREQ_LOBYTE_SHIFT 8
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#define APU_FREQ_HIWORD_SHIFT 0
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#define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000)
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/* APU register 4 */
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#define APUREG_WAVESPACE 4
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#define APU_STEREO 0x8000
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#define APU_USE_SYSMEM 0x4000
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#define APU_PCMBAR_MASK 0x6000
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#define APU_64KPAGE_MASK 0xff00
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/* PCM Base Address Register selection */
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#define APU_PCMBAR_SHIFT 13
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/* 64KW (==128KB) Page */
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#define APU_64KPAGE_SHIFT 8
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/* APU register 5 - 7 */
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#define APUREG_CURPTR 5
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#define APUREG_ENDPTR 6
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#define APUREG_LOOPLEN 7
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/* APU register 9 */
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#define APUREG_AMPLITUDE 9
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#define APU_AMPLITUDE_NOW_MASK 0xff00
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#define APU_AMPLITUDE_DEST_MASK 0x00ff
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/* Amplitude now? */
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#define APU_AMPLITUDE_NOW_SHIFT 8
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/* APU register 10 */
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#define APUREG_POSITION 10
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#define APU_RADIUS_MASK 0x00c0
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#define APU_PAN_MASK 0x003f
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/* Radius control. */
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#define APU_RADIUS_SHIFT 6
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#define RADIUS_CENTERCIRCLE 0
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#define RADIUS_MIDDLE 1
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#define RADIUS_OUTSIDE 2
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/* Polar pan. */
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#define APU_PAN_SHIFT 0
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#define PAN_RIGHT 0x00
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#define PAN_FRONT 0x08
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#define PAN_LEFT 0x10
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/* -----------------------------
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* Limits.
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*/
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#define WPWA_MAX ((1 << 22) - 1)
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#define WPWA_MAXADDR ((1 << 23) - 1)
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#define MAESTRO_MAXADDR ((1 << 28) - 1)
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#endif /* MAESTRO_REG_H_INCLUDED */
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