b6777295a6
same time. o) Remove some unused trivial uart functions from octeon_machdep now that the uart part is fully working and they are unused. o) Use __func__ instead of __FUNCTION__. o) Use intr_*() instead of other routines that do the same thing. o) Remove some duplicate printfs from the Octeon port, as well as duplicate setting of Maxmem. o) Use the right frequency divider on Octeon. o) Use PCPU_GET(cpuid) consistently to get the cpuid of the running core. o) Remove some unused macros in the Octeon port. o) Use mips_sync() around use of the global dpcpu, whose value may not be visible to APs at first. o) When loading the first thread's stack, use macros to make the code correct for n64 as well. o) Remove stub, do-nothing FAU init/enable/disable functions from the RGMX driver.
858 lines
24 KiB
C
858 lines
24 KiB
C
/*-
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* Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/imgact.h>
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#include <sys/bio.h>
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#include <sys/buf.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/cons.h>
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#include <sys/exec.h>
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#include <sys/ucontext.h>
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#include <sys/proc.h>
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#include <sys/kdb.h>
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#include <sys/ptrace.h>
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#include <sys/reboot.h>
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#include <sys/signalvar.h>
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#include <sys/sysent.h>
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#include <sys/sysproto.h>
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#include <sys/user.h>
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#include <vm/vm.h>
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#include <vm/vm_object.h>
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#include <vm/vm_page.h>
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#include <vm/vm_pager.h>
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#include <machine/atomic.h>
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#include <machine/cache.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <machine/cpuregs.h>
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#include <machine/cpufunc.h>
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#include <mips/cavium/octeon_pcmap_regs.h>
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#include <machine/hwfunc.h>
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#include <machine/intr_machdep.h>
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#include <machine/locore.h>
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#include <machine/md_var.h>
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#include <machine/pcpu.h>
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#include <machine/pte.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#if defined(__mips_n64)
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#define MAX_APP_DESC_ADDR 0xffffffffafffffff
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#else
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#define MAX_APP_DESC_ADDR 0xafffffff
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#endif
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extern int *edata;
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extern int *end;
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uint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip);
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void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip);
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static void octeon_boot_params_init(register_t ptr);
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static uint64_t ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx);
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static uint64_t ciu_get_intr_en_reg_addr(int core_num, int intx, int enx);
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static __inline void
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mips_wr_ebase(u_int32_t a0)
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{
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__asm __volatile("mtc0 %[a0], $15, 1 ;"
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:
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: [a0] "r"(a0));
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mips_barrier();
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}
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void
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platform_cpu_init()
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{
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/* Nothing special yet */
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}
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/*
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* Perform a board-level soft-reset.
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*/
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void
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platform_reset(void)
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{
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oct_write64(OCTEON_CIU_SOFT_RST, 1);
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}
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void
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octeon_led_write_char(int char_position, char val)
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{
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uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
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if (!octeon_board_real())
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return;
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char_position &= 0x7; /* only 8 chars */
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ptr += char_position;
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oct_write8_x8(ptr, val);
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}
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void
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octeon_led_write_char0(char val)
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{
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uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
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if (!octeon_board_real())
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return;
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oct_write8_x8(ptr, val);
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}
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void
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octeon_led_write_hexchar(int char_position, char hexval)
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{
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uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
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char char1, char2;
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if (!octeon_board_real())
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return;
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char1 = (hexval >> 4) & 0x0f; char1 = (char1 < 10)?char1+'0':char1+'7';
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char2 = (hexval & 0x0f); char2 = (char2 < 10)?char2+'0':char2+'7';
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char_position &= 0x7; /* only 8 chars */
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if (char_position > 6)
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char_position = 6;
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ptr += char_position;
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oct_write8_x8(ptr, char1);
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ptr++;
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oct_write8_x8(ptr, char2);
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}
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void
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octeon_led_write_string(const char *str)
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{
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uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
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int i;
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if (!octeon_board_real())
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return;
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for (i=0; i<8; i++, ptr++) {
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if (str && *str)
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oct_write8_x8(ptr, *str++);
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else
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oct_write8_x8(ptr, ' ');
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oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
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}
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}
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static char progress[8] = { '-', '/', '|', '\\', '-', '/', '|', '\\'};
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void
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octeon_led_run_wheel(int *prog_count, int led_position)
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{
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if (!octeon_board_real())
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return;
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octeon_led_write_char(led_position, progress[*prog_count]);
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*prog_count += 1;
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*prog_count &= 0x7;
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}
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void
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octeon_led_write_hex(uint32_t wl)
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{
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char nbuf[80];
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sprintf(nbuf, "%X", wl);
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octeon_led_write_string(nbuf);
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}
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/*
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* octeon_debug_symbol
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*
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* Does nothing.
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* Used to mark the point for simulator to begin tracing
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*/
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void
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octeon_debug_symbol(void)
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{
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}
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void
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octeon_ciu_stop_gtimer(int timer)
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{
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oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), 0ll);
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}
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void
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octeon_ciu_start_gtimer(int timer, u_int one_shot, uint64_t time_cycles)
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{
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octeon_ciu_gentimer gentimer;
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gentimer.word64 = 0;
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gentimer.bits.one_shot = one_shot;
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gentimer.bits.len = time_cycles - 1;
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oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), gentimer.word64);
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}
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/*
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* octeon_ciu_reset
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*
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* Shutdown all CIU to IP2, IP3 mappings
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*/
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void
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octeon_ciu_reset(void)
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{
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octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_0);
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octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_1);
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octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_2);
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octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_3);
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ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0);
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ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_1);
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ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0);
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ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1);
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ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0, 0ll);
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ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0, 0ll);
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ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1, 0ll);
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}
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/*
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* mips_disable_interrupt_controllers
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*
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* Disable interrupts in the CPU controller
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*/
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void
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mips_disable_interrupt_controls(void)
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{
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/*
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* Disable interrupts in CIU.
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*/
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octeon_ciu_reset();
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}
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/*
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* ciu_get_intr_sum_reg_addr
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*/
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static uint64_t
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ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx)
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{
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uint64_t ciu_intr_sum_reg_addr;
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if (enx == CIU_EN_0)
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ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_BASE_ADDR +
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(core_num * 0x10) + (intx * 0x8);
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else
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ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_INT1_ADDR;
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return (ciu_intr_sum_reg_addr);
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}
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/*
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* ciu_get_intr_en_reg_addr
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*/
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static uint64_t
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ciu_get_intr_en_reg_addr(int core_num, int intx, int enx)
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{
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uint64_t ciu_intr_reg_addr;
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ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR +
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((enx == 0) ? 0x0 : 0x8) + (intx * 0x10) + (core_num * 0x20);
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return (ciu_intr_reg_addr);
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}
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/*
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* ciu_get_intr_reg_addr
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*
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* 200 ---int0,en0 ip2
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* 208 ---int0,en1 ip2 ----> this is wrong... this is watchdog
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*
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* 210 ---int0,en0 ip3 --
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* 218 ---int0,en1 ip3 ----> same here.. .this is watchdog... right?
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*
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* 220 ---int1,en0 ip2
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* 228 ---int1,en1 ip2
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* 230 ---int1,en0 ip3 --
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* 238 ---int1,en1 ip3
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*
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*/
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uint64_t
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ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip)
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{
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uint64_t ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR;
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/* XXX kasserts? */
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if (enx < CIU_EN_0 || enx > CIU_EN_1) {
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printf("%s: invalid enx value %d, should be %d or %d\n",
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__func__, enx, CIU_EN_0, CIU_EN_1);
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return 0;
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}
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if (intx < CIU_INT_0 || intx > CIU_INT_1) {
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printf("%s: invalid intx value %d, should be %d or %d\n",
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__func__, enx, CIU_INT_0, CIU_INT_1);
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return 0;
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}
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if (ciu_ip < CIU_MIPS_IP2 || ciu_ip > CIU_MIPS_IP3) {
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printf("%s: invalid ciu_ip value %d, should be %d or %d\n",
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__func__, ciu_ip, CIU_MIPS_IP2, CIU_MIPS_IP3);
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return 0;
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}
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ciu_intr_reg_addr += (enx * 0x8);
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ciu_intr_reg_addr += (ciu_ip * 0x10);
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ciu_intr_reg_addr += (intx * 0x20);
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return (ciu_intr_reg_addr);
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}
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/*
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* ciu_get_int_summary
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*/
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uint64_t
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ciu_get_int_summary(int core_num, int intx, int enx)
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{
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uint64_t ciu_intr_sum_reg_addr;
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if (core_num == CIU_THIS_CORE)
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core_num = octeon_get_core_num();
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ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx);
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return (oct_read64(ciu_intr_sum_reg_addr));
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}
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//#define DEBUG_CIU 1
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#ifdef DEBUG_CIU
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#define DEBUG_CIU_SUM 1
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#define DEBUG_CIU_EN 1
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#endif
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/*
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* ciu_clear_int_summary
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*/
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void
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ciu_clear_int_summary(int core_num, int intx, int enx, uint64_t write_bits)
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{
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uint32_t cpu_status_bits;
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uint64_t ciu_intr_sum_reg_addr;
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//#define DEBUG_CIU_SUM 1
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#ifdef DEBUG_CIU_SUM
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uint64_t ciu_intr_sum_bits;
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#endif
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if (core_num == CIU_THIS_CORE) {
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core_num = octeon_get_core_num();
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}
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#ifdef DEBUG_CIU_SUM
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printf(" CIU: core %u clear sum IntX %u Enx %u Bits: 0x%llX\n",
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core_num, intx, enx, write_bits);
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#endif
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cpu_status_bits = intr_disable();
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ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx);
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#ifdef DEBUG_CIU_SUM
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ciu_intr_sum_bits = oct_read64(ciu_intr_sum_reg_addr); /* unneeded dummy read */
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printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
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cpu_status_bits, ciu_intr_sum_reg_addr, ciu_intr_sum_bits,
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ciu_intr_sum_bits | write_bits);
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#endif
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oct_write64(ciu_intr_sum_reg_addr, write_bits);
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oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
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#ifdef DEBUG_CIU_SUM
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printf(" Readback: 0x%llX\n\n ", (uint64_t) oct_read64(ciu_intr_sum_reg_addr));
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#endif
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intr_restore(cpu_status_bits);
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}
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/*
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* ciu_disable_intr
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*/
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void
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ciu_disable_intr(int core_num, int intx, int enx)
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{
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uint32_t cpu_status_bits;
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uint64_t ciu_intr_reg_addr;
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if (core_num == CIU_THIS_CORE)
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core_num = octeon_get_core_num();
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cpu_status_bits = intr_disable();
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ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
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oct_read64(ciu_intr_reg_addr); /* Dummy read */
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oct_write64(ciu_intr_reg_addr, 0LL);
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oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
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intr_restore(cpu_status_bits);
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}
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void
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ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip)
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{
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uint64_t ciu_intr_reg_addr;
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uint64_t ciu_intr_bits;
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if (core_num == CIU_THIS_CORE) {
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core_num = octeon_get_core_num();
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}
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#ifndef OCTEON_SMP_1
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ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
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#else
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ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip);
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#endif
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if (!ciu_intr_reg_addr) {
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printf("Bad call to %s\n", __func__);
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while(1);
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return;
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}
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ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
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printf(" CIU core %d int: %d en: %d ip: %d Add: %#llx enabled: %#llx SR: %x\n",
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core_num, intx, enx, ciu_ip, (unsigned long long)ciu_intr_reg_addr,
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(unsigned long long)ciu_intr_bits, mips_rd_status());
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}
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/*
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* ciu_enable_interrupts
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*/
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void ciu_enable_interrupts(int core_num, int intx, int enx,
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uint64_t set_these_interrupt_bits, int ciu_ip)
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{
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uint32_t cpu_status_bits;
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uint64_t ciu_intr_reg_addr;
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uint64_t ciu_intr_bits;
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if (core_num == CIU_THIS_CORE)
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core_num = octeon_get_core_num();
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//#define DEBUG_CIU_EN 1
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#ifdef DEBUG_CIU_EN
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printf(" CIU: core %u enabling Intx %u Enx %u IP %d Bits: 0x%llX\n",
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core_num, intx, enx, ciu_ip, set_these_interrupt_bits);
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#endif
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|
|
cpu_status_bits = intr_disable();
|
|
|
|
#ifndef OCTEON_SMP_1
|
|
ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
|
|
#else
|
|
ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip);
|
|
#endif
|
|
|
|
if (!ciu_intr_reg_addr) {
|
|
printf("Bad call to %s\n", __func__);
|
|
while(1);
|
|
return; /* XXX */
|
|
}
|
|
|
|
ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
|
|
|
|
#ifdef DEBUG_CIU_EN
|
|
printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
|
|
cpu_status_bits, ciu_intr_reg_addr, ciu_intr_bits, ciu_intr_bits | set_these_interrupt_bits);
|
|
#endif
|
|
ciu_intr_bits |= set_these_interrupt_bits;
|
|
oct_write64(ciu_intr_reg_addr, ciu_intr_bits);
|
|
#ifdef SMP
|
|
mips_wbflush();
|
|
#endif
|
|
oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
|
|
|
|
#ifdef DEBUG_CIU_EN
|
|
printf(" Readback: 0x%llX\n\n ",
|
|
(uint64_t)oct_read64(ciu_intr_reg_addr));
|
|
#endif
|
|
|
|
intr_restore(cpu_status_bits);
|
|
}
|
|
|
|
unsigned long
|
|
octeon_get_clock_rate(void)
|
|
{
|
|
return octeon_cpu_clock;
|
|
}
|
|
|
|
static void
|
|
octeon_memory_init(void)
|
|
{
|
|
uint32_t realmem_bytes;
|
|
|
|
if (octeon_board_real()) {
|
|
realmem_bytes = (octeon_dram - PAGE_SIZE);
|
|
realmem_bytes &= ~(PAGE_SIZE - 1);
|
|
} else {
|
|
/* Simulator we limit to 96 meg */
|
|
realmem_bytes = (96 << 20);
|
|
}
|
|
/* phys_avail regions are in bytes */
|
|
phys_avail[0] = (MIPS_KSEG0_TO_PHYS((vm_offset_t)&end) + PAGE_SIZE) & ~(PAGE_SIZE - 1);
|
|
if (octeon_board_real()) {
|
|
if (realmem_bytes > OCTEON_DRAM_FIRST_256_END)
|
|
phys_avail[1] = OCTEON_DRAM_FIRST_256_END;
|
|
else
|
|
phys_avail[1] = realmem_bytes;
|
|
realmem_bytes -= OCTEON_DRAM_FIRST_256_END;
|
|
realmem_bytes &= ~(PAGE_SIZE - 1);
|
|
} else {
|
|
/* Simulator gets 96Meg period. */
|
|
phys_avail[1] = (96 << 20);
|
|
}
|
|
/*-
|
|
* Octeon Memory looks as follows:
|
|
* PA
|
|
* 0000 0000 to 0x0 0000 0000 0000
|
|
* 0FFF FFFF First 256 MB memory Maps to 0x0 0000 0FFF FFFF
|
|
*
|
|
* 1000 0000 to 0x1 0000 1000 0000
|
|
* 1FFF FFFF Uncached Bu I/O space.converted to 0x1 0000 1FFF FFFF
|
|
*
|
|
* 2FFF FFFF to Cached 0x0 0000 2000 0000
|
|
* FFFF FFFF all dram mem above the first 512M 0x3 FFFF FFFF FFFF
|
|
*
|
|
*/
|
|
physmem = btoc(phys_avail[1] - phys_avail[0]);
|
|
if ((octeon_board_real()) &&
|
|
(realmem_bytes > OCTEON_DRAM_FIRST_256_END)) {
|
|
/* take out the upper non-cached 1/2 */
|
|
realmem_bytes -= OCTEON_DRAM_FIRST_256_END;
|
|
realmem_bytes &= ~(PAGE_SIZE - 1);
|
|
/* Now map the rest of the memory */
|
|
phys_avail[2] = 0x20000000;
|
|
phys_avail[3] = ((uint32_t) 0x20000000 + realmem_bytes);
|
|
physmem += btoc(phys_avail[3] - phys_avail[2]);
|
|
}
|
|
realmem = physmem;
|
|
|
|
printf("Total DRAM Size %#X\n", (uint32_t) octeon_dram);
|
|
printf("Bank 0 = %#08lX -> %#08lX\n", (long)phys_avail[0], (long)phys_avail[1]);
|
|
printf("Bank 1 = %#08lX -> %#08lX\n", (long)phys_avail[2], (long)phys_avail[3]);
|
|
}
|
|
|
|
void
|
|
platform_start(__register_t a0, __register_t a1, __register_t a2 __unused,
|
|
__register_t a3)
|
|
{
|
|
uint64_t platform_counter_freq;
|
|
|
|
/* Initialize pcpu stuff */
|
|
mips_pcpu0_init();
|
|
mips_timer_early_init(OCTEON_CLOCK_DEFAULT);
|
|
cninit();
|
|
|
|
octeon_ciu_reset();
|
|
octeon_boot_params_init(a3);
|
|
bootverbose = 1;
|
|
|
|
/*
|
|
* For some reason on the cn38xx simulator ebase register is set to
|
|
* 0x80001000 at bootup time. Move it back to the default, but
|
|
* when we move to having support for multiple executives, we need
|
|
* to rethink this.
|
|
*/
|
|
mips_wr_ebase(0x80000000);
|
|
|
|
octeon_memory_init();
|
|
init_param1();
|
|
init_param2(physmem);
|
|
mips_cpu_init();
|
|
pmap_bootstrap();
|
|
mips_proc0_init();
|
|
mutex_init();
|
|
kdb_init();
|
|
#ifdef KDB
|
|
if (boothowto & RB_KDB)
|
|
kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
|
|
#endif
|
|
platform_counter_freq = octeon_get_clock_rate();
|
|
mips_timer_init_params(platform_counter_freq, 0);
|
|
|
|
#ifdef SMP
|
|
/*
|
|
* Clear any pending IPIs and enable the IPI interrupt.
|
|
*/
|
|
oct_write64(OCTEON_CIU_MBOX_CLRX(0), 0xffffffff);
|
|
ciu_enable_interrupts(0, CIU_INT_1, CIU_EN_0, OCTEON_CIU_ENABLE_MBOX_INTR, CIU_MIPS_IP3);
|
|
#endif
|
|
}
|
|
|
|
/* impSTART: This stuff should move back into the Cavium SDK */
|
|
/*
|
|
****************************************************************************************
|
|
*
|
|
* APP/BOOT DESCRIPTOR STUFF
|
|
*
|
|
****************************************************************************************
|
|
*/
|
|
|
|
/* Define the struct that is initialized by the bootloader used by the
|
|
* startup code.
|
|
*
|
|
* Copyright (c) 2004, 2005, 2006 Cavium Networks.
|
|
*
|
|
* The authors hereby grant permission to use, copy, modify, distribute,
|
|
* and license this software and its documentation for any purpose, provided
|
|
* that existing copyright notices are retained in all copies and that this
|
|
* notice is included verbatim in any distributions. No written agreement,
|
|
* license, or royalty fee is required for any of the authorized uses.
|
|
* Modifications to this software may be copyrighted by their authors
|
|
* and need not follow the licensing terms described here, provided that
|
|
* the new terms are clearly indicated on the first page of each file where
|
|
* they apply.
|
|
*/
|
|
|
|
#define OCTEON_CURRENT_DESC_VERSION 6
|
|
#define OCTEON_ARGV_MAX_ARGS (64)
|
|
#define OCTOEN_SERIAL_LEN 20
|
|
|
|
|
|
typedef struct {
|
|
/* Start of block referenced by assembly code - do not change! */
|
|
uint32_t desc_version;
|
|
uint32_t desc_size;
|
|
|
|
uint64_t stack_top;
|
|
uint64_t heap_base;
|
|
uint64_t heap_end;
|
|
uint64_t entry_point; /* Only used by bootloader */
|
|
uint64_t desc_vaddr;
|
|
/* End of This block referenced by assembly code - do not change! */
|
|
|
|
uint32_t exception_base_addr;
|
|
uint32_t stack_size;
|
|
uint32_t heap_size;
|
|
uint32_t argc; /* Argc count for application */
|
|
uint32_t argv[OCTEON_ARGV_MAX_ARGS];
|
|
uint32_t flags;
|
|
uint32_t core_mask;
|
|
uint32_t dram_size; /**< DRAM size in megabyes */
|
|
uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/
|
|
uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */
|
|
uint32_t eclock_hz; /**< CPU clock speed, in hz */
|
|
uint32_t dclock_hz; /**< DRAM clock speed, in hz */
|
|
uint32_t spi_clock_hz; /**< SPI4 clock in hz */
|
|
uint16_t board_type;
|
|
uint8_t board_rev_major;
|
|
uint8_t board_rev_minor;
|
|
uint16_t chip_type;
|
|
uint8_t chip_rev_major;
|
|
uint8_t chip_rev_minor;
|
|
char board_serial_number[OCTOEN_SERIAL_LEN];
|
|
uint8_t mac_addr_base[6];
|
|
uint8_t mac_addr_count;
|
|
uint64_t cvmx_desc_vaddr;
|
|
} octeon_boot_descriptor_t;
|
|
|
|
|
|
typedef struct {
|
|
uint32_t major_version;
|
|
uint32_t minor_version;
|
|
|
|
uint64_t stack_top;
|
|
uint64_t heap_base;
|
|
uint64_t heap_end;
|
|
uint64_t desc_vaddr;
|
|
|
|
uint32_t exception_base_addr;
|
|
uint32_t stack_size;
|
|
uint32_t flags;
|
|
uint32_t core_mask;
|
|
uint32_t dram_size; /**< DRAM size in megabyes */
|
|
uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/
|
|
uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */
|
|
uint32_t eclock_hz; /**< CPU clock speed, in hz */
|
|
uint32_t dclock_hz; /**< DRAM clock speed, in hz */
|
|
uint32_t spi_clock_hz; /**< SPI4 clock in hz */
|
|
uint16_t board_type;
|
|
uint8_t board_rev_major;
|
|
uint8_t board_rev_minor;
|
|
uint16_t chip_type;
|
|
uint8_t chip_rev_major;
|
|
uint8_t chip_rev_minor;
|
|
char board_serial_number[OCTOEN_SERIAL_LEN];
|
|
uint8_t mac_addr_base[6];
|
|
uint8_t mac_addr_count;
|
|
} cvmx_bootinfo_t;
|
|
|
|
uint32_t octeon_cpu_clock;
|
|
uint64_t octeon_dram;
|
|
uint32_t octeon_bd_ver = 0, octeon_cvmx_bd_ver = 0, octeon_board_rev_major, octeon_board_rev_minor, octeon_board_type;
|
|
uint8_t octeon_mac_addr[6] = { 0 };
|
|
int octeon_core_mask, octeon_mac_addr_count;
|
|
int octeon_chip_rev_major = 0, octeon_chip_rev_minor = 0, octeon_chip_type = 0;
|
|
|
|
static octeon_boot_descriptor_t *app_desc_ptr;
|
|
static cvmx_bootinfo_t *cvmx_desc_ptr;
|
|
|
|
#define OCTEON_BOARD_TYPE_NONE 0
|
|
#define OCTEON_BOARD_TYPE_SIM 1
|
|
#define OCTEON_BOARD_TYPE_CN3010_EVB_HS5 11
|
|
|
|
#define OCTEON_CLOCK_MIN (100 * 1000 * 1000)
|
|
#define OCTEON_CLOCK_MAX (800 * 1000 * 1000)
|
|
#define OCTEON_DRAM_DEFAULT (256 * 1024 * 1024)
|
|
#define OCTEON_DRAM_MIN 30
|
|
#define OCTEON_DRAM_MAX 3000
|
|
|
|
|
|
int
|
|
octeon_board_real(void)
|
|
{
|
|
switch (octeon_board_type) {
|
|
case OCTEON_BOARD_TYPE_NONE:
|
|
case OCTEON_BOARD_TYPE_SIM:
|
|
return 0;
|
|
case OCTEON_BOARD_TYPE_CN3010_EVB_HS5:
|
|
/*
|
|
* XXX
|
|
* The CAM-0100 identifies itself as type 11, revision 0.0,
|
|
* despite its being rather real. Disable the revision check
|
|
* for type 11.
|
|
*/
|
|
return 1;
|
|
default:
|
|
if (octeon_board_rev_major == 0)
|
|
return 0;
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
static void
|
|
octeon_process_app_desc_ver_unknown(void)
|
|
{
|
|
printf(" Unknown Boot-Descriptor: Using Defaults\n");
|
|
|
|
octeon_cpu_clock = OCTEON_CLOCK_DEFAULT;
|
|
octeon_dram = OCTEON_DRAM_DEFAULT;
|
|
octeon_board_rev_major = octeon_board_rev_minor = octeon_board_type = 0;
|
|
octeon_core_mask = 1;
|
|
octeon_chip_type = octeon_chip_rev_major = octeon_chip_rev_minor = 0;
|
|
octeon_mac_addr[0] = 0x00; octeon_mac_addr[1] = 0x0f;
|
|
octeon_mac_addr[2] = 0xb7; octeon_mac_addr[3] = 0x10;
|
|
octeon_mac_addr[4] = 0x09; octeon_mac_addr[5] = 0x06;
|
|
octeon_mac_addr_count = 1;
|
|
}
|
|
|
|
static int
|
|
octeon_process_app_desc_ver_6(void)
|
|
{
|
|
/* XXX Why is 0x00000000ffffffffULL a bad value? */
|
|
if (app_desc_ptr->cvmx_desc_vaddr == 0 ||
|
|
app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) {
|
|
printf ("Bad cvmx_desc_ptr %p\n", cvmx_desc_ptr);
|
|
return 1;
|
|
}
|
|
cvmx_desc_ptr =
|
|
(cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr;
|
|
cvmx_desc_ptr =
|
|
(cvmx_bootinfo_t *) ((intptr_t)cvmx_desc_ptr | MIPS_KSEG0_START);
|
|
octeon_cvmx_bd_ver = (cvmx_desc_ptr->major_version * 100) +
|
|
cvmx_desc_ptr->minor_version;
|
|
if (cvmx_desc_ptr->major_version != 1) {
|
|
panic("Incompatible CVMX descriptor from bootloader: %d.%d %p\n",
|
|
(int) cvmx_desc_ptr->major_version,
|
|
(int) cvmx_desc_ptr->minor_version, cvmx_desc_ptr);
|
|
}
|
|
|
|
octeon_core_mask = cvmx_desc_ptr->core_mask;
|
|
octeon_cpu_clock = cvmx_desc_ptr->eclock_hz;
|
|
octeon_board_type = cvmx_desc_ptr->board_type;
|
|
octeon_board_rev_major = cvmx_desc_ptr->board_rev_major;
|
|
octeon_board_rev_minor = cvmx_desc_ptr->board_rev_minor;
|
|
octeon_chip_type = cvmx_desc_ptr->chip_type;
|
|
octeon_chip_rev_major = cvmx_desc_ptr->chip_rev_major;
|
|
octeon_chip_rev_minor = cvmx_desc_ptr->chip_rev_minor;
|
|
octeon_mac_addr[0] = cvmx_desc_ptr->mac_addr_base[0];
|
|
octeon_mac_addr[1] = cvmx_desc_ptr->mac_addr_base[1];
|
|
octeon_mac_addr[2] = cvmx_desc_ptr->mac_addr_base[2];
|
|
octeon_mac_addr[3] = cvmx_desc_ptr->mac_addr_base[3];
|
|
octeon_mac_addr[4] = cvmx_desc_ptr->mac_addr_base[4];
|
|
octeon_mac_addr[5] = cvmx_desc_ptr->mac_addr_base[5];
|
|
octeon_mac_addr_count = cvmx_desc_ptr->mac_addr_count;
|
|
|
|
if (app_desc_ptr->dram_size > 16*1024*1024)
|
|
octeon_dram = (uint64_t)app_desc_ptr->dram_size;
|
|
else
|
|
octeon_dram = (uint64_t)app_desc_ptr->dram_size << 20;
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
octeon_boot_params_init(register_t ptr)
|
|
{
|
|
int bad_desc = 1;
|
|
|
|
if (ptr != 0 && ptr < MAX_APP_DESC_ADDR) {
|
|
app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr;
|
|
octeon_bd_ver = app_desc_ptr->desc_version;
|
|
if (app_desc_ptr->desc_version < 6)
|
|
panic("Your boot code is too old to be supported.\n");
|
|
if (app_desc_ptr->desc_version >= 6)
|
|
bad_desc = octeon_process_app_desc_ver_6();
|
|
}
|
|
if (bad_desc)
|
|
octeon_process_app_desc_ver_unknown();
|
|
|
|
printf("Boot Descriptor Ver: %u -> %u/%u",
|
|
octeon_bd_ver, octeon_cvmx_bd_ver/100, octeon_cvmx_bd_ver%100);
|
|
printf(" CPU clock: %uMHz Core Mask: %#x\n", octeon_cpu_clock/1000000, octeon_core_mask);
|
|
printf(" Dram: %u MB", (uint32_t)(octeon_dram >> 20));
|
|
printf(" Board Type: %u Revision: %u/%u\n",
|
|
octeon_board_type, octeon_board_rev_major, octeon_board_rev_minor);
|
|
printf(" Octeon Chip: %u Rev %u/%u",
|
|
octeon_chip_type, octeon_chip_rev_major, octeon_chip_rev_minor);
|
|
|
|
printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n",
|
|
octeon_mac_addr[0], octeon_mac_addr[1], octeon_mac_addr[2],
|
|
octeon_mac_addr[3], octeon_mac_addr[4], octeon_mac_addr[5],
|
|
octeon_mac_addr_count);
|
|
}
|
|
/* impEND: This stuff should move back into the Cavium SDK */
|