d381cdd7a8
- Major update to xlr_i2c.c: do multi-byte ops correctly, remove unnecessary code, add mutex to protect bus operations, style(9) fixes. - Drivers for I2C devices on XLR/XLS engineering boards, ds1374u RTC, max6657 temparature sensor and at24co2n EEPROM. Submitted by: Sreekanth M. S. (kanthms at netlogicmicro com)
251 lines
7.1 KiB
C
251 lines
7.1 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD
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* $FreeBSD$
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*/
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#ifndef _RMI_BOARD_H_
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#define _RMI_BOARD_H_
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/*
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* Engineering boards have a major/minor number in their EEPROM to
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* identify their configuration
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*/
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#define RMI_XLR_BOARD_ARIZONA_I 1
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#define RMI_XLR_BOARD_ARIZONA_II 2
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#define RMI_XLR_BOARD_ARIZONA_III 3
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#define RMI_XLR_BOARD_ARIZONA_IV 4
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#define RMI_XLR_BOARD_ARIZONA_V 5
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#define RMI_XLR_BOARD_ARIZONA_VI 6
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#define RMI_XLR_BOARD_ARIZONA_VII 7
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#define RMI_XLR_BOARD_ARIZONA_VIII 8
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#define RMI_XLR_BOARD_ARIZONA_XI 11
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#define RMI_XLR_BOARD_ARIZONA_XII 12
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/*
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* RMI Chips - Values in Processor ID field
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*/
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#define RMI_CHIP_XLR732 0x00
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#define RMI_CHIP_XLR716 0x02
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#define RMI_CHIP_XLR308 0x06
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#define RMI_CHIP_XLR532 0x09
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/*
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* XLR C revisions
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*/
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#define RMI_CHIP_XLR308_C 0x0F
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#define RMI_CHIP_XLR508_C 0x0b
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#define RMI_CHIP_XLR516_C 0x0a
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#define RMI_CHIP_XLR532_C 0x08
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/*
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* XLS processors
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*/
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#define RMI_CHIP_XLS408 0x88 /* Lite "Condor" */
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#define RMI_CHIP_XLS608 0x80 /* Internal */
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#define RMI_CHIP_XLS404 0x8c /* Lite "Condor" */
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#define RMI_CHIP_XLS208 0x8e
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#define RMI_CHIP_XLS204 0x8f
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#define RMI_CHIP_XLS108 0xce
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#define RMI_CHIP_XLS104 0xcf
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/*
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* XLS B revision chips
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*/
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#define RMI_CHIP_XLS616_B0 0x40
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#define RMI_CHIP_XLS608_B0 0x4a
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#define RMI_CHIP_XLS416_B0 0x44
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#define RMI_CHIP_XLS412_B0 0x4c
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#define RMI_CHIP_XLS408_B0 0x4e
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#define RMI_CHIP_XLS404_B0 0x4f
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/*
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* The XLS product line has chip versions 0x4x and 0x8x
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*/
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static __inline unsigned int
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xlr_is_xls(void)
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{
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uint32_t prid = mips_rd_prid();
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return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 ||
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(prid & 0xf000) == 0xc000);
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}
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/*
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* The last byte of the processor id field is revision
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*/
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static __inline unsigned int
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xlr_revision(void)
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{
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return (mips_rd_prid() & 0xff);
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}
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/*
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* The 15:8 byte of the PR Id register is the Processor ID
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*/
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static __inline unsigned int
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xlr_processor_id(void)
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{
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return ((mips_rd_prid() & 0xff00) >> 8);
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}
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/*
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* The processor is XLR and C-Series
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*/
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static __inline unsigned int
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xlr_is_c_revision(void)
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{
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int processor_id = xlr_processor_id();
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int revision_id = xlr_revision();
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switch (processor_id) {
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/*
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* These are the relevant PIDs for XLR
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* steppings (hawk and above). For these,
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* PIDs, Rev-Ids of [5-9] indicate 'C'.
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*/
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case RMI_CHIP_XLR308_C:
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case RMI_CHIP_XLR508_C:
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case RMI_CHIP_XLR516_C:
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case RMI_CHIP_XLR532_C:
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case RMI_CHIP_XLR716:
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case RMI_CHIP_XLR732:
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if (revision_id >= 5 && revision_id <= 9)
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return (1);
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default:
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return (0);
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}
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return (0);
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}
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/*
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* RMI Engineering boards which are PCI cards
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* These should come up in PCI device mode (not yet)
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*/
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static __inline int
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xlr_board_pci(int board_major)
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{
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return ((board_major == RMI_XLR_BOARD_ARIZONA_III) ||
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(board_major == RMI_XLR_BOARD_ARIZONA_V));
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}
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static __inline int
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xlr_is_xls1xx(void)
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{
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uint32_t chipid = xlr_processor_id();
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return (chipid == 0xce || chipid == 0xcf);
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}
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static __inline int
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xlr_is_xls2xx(void)
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{
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uint32_t chipid = xlr_processor_id();
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return (chipid == 0x8e || chipid == 0x8f);
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}
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static __inline int
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xlr_is_xls4xx_lite(void)
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{
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uint32_t chipid = xlr_processor_id();
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return (chipid == 0x88 || chipid == 0x8c);
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}
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static __inline unsigned int
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xlr_is_xls_b0(void)
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{
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uint32_t chipid = xlr_processor_id();
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return (chipid >= 0x40 && chipid <= 0x4f);
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}
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/* SPI-4 --> 8 ports, 1G MAC --> 4 ports and 10G MAC --> 1 port */
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#define MAX_NA_PORTS 8
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/* all our knowledge of chip and board that cannot be detected run-time goes here */
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enum gmac_block_types { XLR_GMAC, XLR_XGMAC, XLR_SPI4};
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enum gmac_port_types { XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII, XLR_XGMII, XLR_XAUI };
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enum i2c_dev_types { I2C_RTC, I2C_THERMAL, I2C_EEPROM };
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struct xlr_board_info {
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int is_xls;
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int nr_cpus;
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int usb; /* usb enabled ? */
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int cfi; /* compact flash driver for NOR? */
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int ata; /* ata driver */
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int pci_irq;
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struct stn_cc **credit_configs; /* pointer to Core station credits */
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struct bucket_size *bucket_sizes; /* pointer to Core station bucket */
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int *msgmap; /* mapping of message station to devices */
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int gmacports; /* number of gmac ports on the board */
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struct xlr_i2c_dev_t {
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uint32_t addr;
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unsigned int enabled; /* mask of devs enabled */
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int type;
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int unit;
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char *dev_name;
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} xlr_i2c_device[3];
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struct xlr_gmac_block_t { /* refers to the set of GMACs controlled by a
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network accelarator */
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int type; /* see enum gmac_block_types */
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unsigned int enabled; /* mask of ports enabled */
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struct stn_cc *credit_config; /* credit configuration */
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int station_id; /* station id for sending msgs */
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int station_txbase; /* station id for tx */
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int station_rfr; /* free desc bucket */
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int mode; /* see gmac_block_modes */
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uint32_t baseaddr; /* IO base */
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int baseirq; /* first irq for this block, the rest are in sequence */
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int baseinst; /* the first rge unit for this block */
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int num_ports;
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struct xlr_gmac_port {
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int valid;
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int type; /* see enum gmac_port_types */
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uint32_t instance; /* identifies the GMAC to which
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this port is bound to. */
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uint32_t phy_addr;
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uint32_t base_addr;
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uint32_t mii_addr;
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uint32_t pcs_addr;
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uint32_t serdes_addr;
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uint32_t tx_bucket_id;
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uint32_t mdint_id;
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} gmac_port[MAX_NA_PORTS];
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} gmac_block [3];
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};
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extern struct xlr_board_info xlr_board_info;
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int xlr_board_info_setup(void);
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#endif
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