90d90d0c24
variables from i386 assembly language. The syntax is PCPU(member) where member is the capitalized name of the per-cpu variable, without the gd_ prefix. Example: movl %eax,PCPU(CURPROC). The capitalization is due to using the offsets generated by genassym rather than the symbols provided by linking with globals.o. asmacros.h is the wrong place for this but it seemed as good a place as any for now. The old implementation in asnames.h has not been removed because it is still used to de-mangle the symbols used by the C variables for the UP case.
153 lines
4.5 KiB
ArmAsm
153 lines
4.5 KiB
ArmAsm
/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $FreeBSD$
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*/
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/*
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* modified for PC98 by Kakefuda
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*/
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#ifdef PC98
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#define ICU_IMR_OFFSET 2 /* IO_ICU{1,2} + 2 */
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#else
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#define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */
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#endif
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#define ICU_EOI 0x20 /* XXX - define elsewhere */
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_BYTE(irq_num) ((irq_num) >> 3)
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#ifdef AUTO_EOI_1
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#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
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#define OUTB_ICU1
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#else
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#define ENABLE_ICU1 \
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movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
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OUTB_ICU1 /* ... to clear in service bit */
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#define OUTB_ICU1 \
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outb %al,$IO_ICU1
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#endif
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#ifdef AUTO_EOI_2
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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*/
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#define ENABLE_ICU1_AND_2 ENABLE_ICU1
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#else
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#define ENABLE_ICU1_AND_2 \
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movb $ICU_EOI,%al ; /* as above */ \
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outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
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OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
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#endif
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/*
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* Macros for interrupt interrupt entry, call to handler, and exit.
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*/
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#define FAST_INTR(irq_num, vec_name, enable_icus) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; \
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pushl %ds ; \
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pushl %es ; \
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pushl %fs ; \
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mov $KDSEL,%ax ; \
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mov %ax,%ds ; \
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mov %ax,%es ; \
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mov %ax,%fs ; \
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FAKE_MCOUNT((12+ACTUALLY_PUSHED)*4(%esp)) ; \
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incb PCPU(INTR_NESTING_LEVEL) ; \
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pushl _intr_unit + (irq_num) * 4 ; \
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call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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enable_icus ; /* (re)enable ASAP (helps edge trigger?) */ \
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addl $4,%esp ; \
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incl _cnt+V_INTR ; /* book-keeping can wait */ \
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movl _intr_countp + (irq_num) * 4,%eax ; \
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incl (%eax) ; \
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MEXITCOUNT ; \
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jmp _doreti
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/*
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* Slow, threaded interrupts.
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*
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* XXX Most of the parameters here are obsolete. Fix this when we're
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* done.
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* XXX we really shouldn't return via doreti if we just schedule the
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* interrupt handler and don't run anything. We could just do an
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* iret. FIXME.
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*/
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#define INTR(irq_num, vec_name, icu, enable_icus, reg, maybe_extra_ipending) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; \
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pushl %ds ; /* save our data and extra segments ... */ \
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pushl %es ; \
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pushl %fs ; \
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mov $KDSEL,%ax ; /* load kernel ds, es and fs */ \
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mov %ax,%ds ; \
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mov %ax,%es ; \
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mov %ax,%fs ; \
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maybe_extra_ipending ; \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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orb $IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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outb %al,$icu+ICU_IMR_OFFSET ; \
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enable_icus ; \
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incb PCPU(INTR_NESTING_LEVEL) ; \
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__CONCAT(Xresume,irq_num): ; \
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FAKE_MCOUNT(13*4(%esp)) ; /* XXX late to avoid double count */ \
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pushl $irq_num; /* pass the IRQ */ \
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sti ; \
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call _sched_ithd ; \
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addl $4, %esp ; /* discard the parameter */ \
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MEXITCOUNT ; \
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/* We could usually avoid the following jmp by inlining some of */ \
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/* _doreti, but it's probably better to use less cache. */ \
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jmp _doreti /* and catch up inside doreti */
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MCOUNT_LABEL(bintr)
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FAST_INTR(0,fastintr0, ENABLE_ICU1)
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FAST_INTR(1,fastintr1, ENABLE_ICU1)
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FAST_INTR(2,fastintr2, ENABLE_ICU1)
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FAST_INTR(3,fastintr3, ENABLE_ICU1)
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FAST_INTR(4,fastintr4, ENABLE_ICU1)
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FAST_INTR(5,fastintr5, ENABLE_ICU1)
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FAST_INTR(6,fastintr6, ENABLE_ICU1)
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FAST_INTR(7,fastintr7, ENABLE_ICU1)
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FAST_INTR(8,fastintr8, ENABLE_ICU1_AND_2)
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FAST_INTR(9,fastintr9, ENABLE_ICU1_AND_2)
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FAST_INTR(10,fastintr10, ENABLE_ICU1_AND_2)
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FAST_INTR(11,fastintr11, ENABLE_ICU1_AND_2)
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FAST_INTR(12,fastintr12, ENABLE_ICU1_AND_2)
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FAST_INTR(13,fastintr13, ENABLE_ICU1_AND_2)
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FAST_INTR(14,fastintr14, ENABLE_ICU1_AND_2)
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FAST_INTR(15,fastintr15, ENABLE_ICU1_AND_2)
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#define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
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/* Threaded interrupts */
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INTR(0,intr0, IO_ICU1, ENABLE_ICU1, al, CLKINTR_PENDING)
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INTR(1,intr1, IO_ICU1, ENABLE_ICU1, al,)
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INTR(2,intr2, IO_ICU1, ENABLE_ICU1, al,)
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INTR(3,intr3, IO_ICU1, ENABLE_ICU1, al,)
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INTR(4,intr4, IO_ICU1, ENABLE_ICU1, al,)
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INTR(5,intr5, IO_ICU1, ENABLE_ICU1, al,)
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INTR(6,intr6, IO_ICU1, ENABLE_ICU1, al,)
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INTR(7,intr7, IO_ICU1, ENABLE_ICU1, al,)
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INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2, ah,)
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MCOUNT_LABEL(eintr)
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