3154bc4680
These SoCs have CHIPID registers, which store the Chip model, according to the manufacturer; make use of those in order to better identify the chip we're actually running on. If we're unable to read the CHIPID registers for some reason we will use the string "unknown " as a value for hw.model. Reported by: yamori813@yahoo.co.jp Sponsored by: Smartcom - Bulgaria AD
139 lines
4.3 KiB
C
139 lines
4.3 KiB
C
/*-
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* Copyright (c) 2016 Stanislav Galabov.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MTK_SOC_H_
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#define _MTK_SOC_H_
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enum mtk_soc_id {
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MTK_SOC_UNKNOWN,
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MTK_SOC_RT2880,
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MTK_SOC_RT3050,
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MTK_SOC_RT3052,
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MTK_SOC_RT3350,
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MTK_SOC_RT3352,
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MTK_SOC_RT3662,
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MTK_SOC_RT3883,
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MTK_SOC_RT5350,
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MTK_SOC_MT7620A,
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MTK_SOC_MT7620N,
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MTK_SOC_MT7621,
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MTK_SOC_MT7628,
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MTK_SOC_MT7688,
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MTK_SOC_MAX
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};
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#define RT2880_CPU_CLKSEL_OFF 20
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#define RT2880_CPU_CLKSEL_MSK 0x3
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#define RT305X_CPU_CLKSEL_OFF 18
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#define RT305X_CPU_CLKSEL_MSK 0x1
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#define RT3352_CPU_CLKSEL_OFF 8
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#define RT3352_CPU_CLKSEL_MSK 0x1
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#define RT3883_CPU_CLKSEL_OFF 8
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#define RT3883_CPU_CLKSEL_MSK 0x3
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#define RT5350_CPU_CLKSEL_OFF1 8
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#define RT5350_CPU_CLKSEL_OFF2 10
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#define RT5350_CPU_CLKSEL_MSK 0x1
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#define MT7628_CPU_CLKSEL_OFF 6
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#define MT7628_CPU_CLKSEL_MSK 0x1
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#define MT7620_CPU_CLK_AUX0 (1u<<24)
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#define MT7620_CPLL_SW_CFG (1u<<31)
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#define MT7620_PLL_MULT_RATIO_OFF 16
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#define MT7620_PLL_MULT_RATIO_MSK 0x7
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#define MT7620_PLL_MULT_RATIO_BASE 24
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#define MT7620_PLL_DIV_RATIO_OFF 10
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#define MT7620_PLL_DIV_RATIO_MSK 0x3
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#define MT7620_PLL_DIV_RATIO_BASE 2
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#define MT7620_PLL_DIV_RATIO_MAX 8
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#define MT7620_XTAL_40 40
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#define MT7621_USES_MEMDIV (1u<<30)
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#define MT7621_MEMDIV_OFF 4
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#define MT7621_MEMDIV_MSK 0x7f
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#define MT7621_MEMDIV_BASE 1
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#define MT7621_CLKSEL_OFF 6
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#define MT7621_CLKSEL_MSK 0x7
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#define MT7621_CLKSEL_25MHZ_VAL 6
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#define MT7621_CLKSEL_20MHZ_VAL 3
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#define MT7621_CLKSEL_20MHZ 20
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#define MT7621_CLKSEL_25MHZ 25
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#define MT7621_CLK_STS_DIV_OFF 8
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#define MT7621_CLK_STS_MSK 0x1f
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#define MT7621_CLK_STS_BASE 500
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#define MTK_MT7621_CLKDIV_REG 0x5648
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#define MTK_MT7621_CLKDIV_OFF 4
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#define MTK_MT7621_CLKDIV_MSK 0x7f
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#define MTK_MHZ(x) ((x) * 1000 * 1000)
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#define MTK_CPU_CLK_UNKNOWN 0
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#define MTK_CPU_CLK_233MHZ 233333333
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#define MTK_CPU_CLK_250MHZ 250000000
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#define MTK_CPU_CLK_266MHZ 266666666
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#define MTK_CPU_CLK_280MHZ 280000000
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#define MTK_CPU_CLK_300MHZ 300000000
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#define MTK_CPU_CLK_320MHZ 320000000
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#define MTK_CPU_CLK_360MHZ 360000000
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#define MTK_CPU_CLK_384MHZ 384000000
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#define MTK_CPU_CLK_400MHZ 400000000
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#define MTK_CPU_CLK_480MHZ 480000000
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#define MTK_CPU_CLK_500MHZ 500000000
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#define MTK_CPU_CLK_575MHZ 575000000
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#define MTK_CPU_CLK_580MHZ 580000000
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#define MTK_CPU_CLK_600MHZ 600000000
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#define MTK_CPU_CLK_880MHZ 880000000
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#define MTK_UART_CLK_40MHZ 40000000
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#define MTK_UART_CLK_50MHZ 50000000
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#define MTK_UARTDIV_2 2
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#define MTK_UARTDIV_3 3
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#define MTK_DEFAULT_BASE 0x10000000
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#define MTK_RT2880_BASE 0x00300000
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#define MTK_MT7621_BASE 0x1e000000
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#define MTK_DEFAULT_SIZE 0x6000
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extern void mtk_soc_try_early_detect(void);
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extern void mtk_soc_set_cpu_model(void);
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extern uint32_t mtk_soc_get_uartclk(void);
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extern uint32_t mtk_soc_get_cpuclk(void);
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extern uint32_t mtk_soc_get_timerclk(void);
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extern uint32_t mtk_soc_get_socid(void);
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extern int mtk_soc_reset_device(device_t);
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extern int mtk_soc_stop_clock(device_t);
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extern int mtk_soc_start_clock(device_t);
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extern int mtk_soc_assert_reset(device_t);
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extern int mtk_soc_deassert_reset(device_t);
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extern void mtk_soc_reset(void);
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#endif /* _MTK_SOC_H_ */
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