144450f3a9
Approved by: stas (mentor)
68 lines
2.2 KiB
C
68 lines
2.2 KiB
C
/*-
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* Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _A20_CPU_CFG_H_
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#define _A20_CPU_CFG_H_
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#define CPU_CFG_BASE 0xe1c25c00
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#define CPU0_RST_CTRL 0x0040
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#define CPU0_CTRL_REG 0x0044
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#define CPU0_STATUS_REG 0x0048
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#define CPU1_RST_CTRL 0x0080
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#define CPU1_CTRL_REG 0x0084
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#define CPU1_STATUS_REG 0x0088
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#define GENER_CTRL_REG 0x0184
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#define EVENT_IN_REG 0x0190
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#define PRIVATE_REG 0x01a4
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#define IDLE_CNT0_LOW_REG 0x0200
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#define IDLE_CNT0_HIGH_REG 0x0204
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#define IDLE_CNT0_CTRL_REG 0x0208
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#define IDLE_CNT1_LOW_REG 0x0210
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#define IDLE_CNT1_HIGH_REG 0x0214
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#define IDLE_CNT1_CTRL_REG 0x0218
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#define OSC24M_CNT64_CTRL_REG 0x0280
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#define OSC24M_CNT64_LOW_REG 0x0284
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#define OSC24M_CNT64_HIGH_REG 0x0288
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#define LOSC_CNT64_CTRL_REG 0x0290
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#define LOSC_CNT64_LOW_REG 0x0294
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#define LOSC_CNT64_HIGH_REG 0x0298
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#define CNT64_RL_EN 0x02 /* read latch enable */
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uint64_t a20_read_counter64(void);
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#endif /* _A20_CPU_CFG_H_ */
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