315 lines
9.5 KiB
C
315 lines
9.5 KiB
C
/*
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* Copyright (c) 1999, Traakan Software
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define WX_VENDOR_INTEL 0x8086
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#define WX_PRODUCT_82452 0x1000
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#define WX_MMBA 0x10
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#define MWI 0x10 /* Memory Write Invalidate */
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#define WX_CACHELINE_SIZE 0x20
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/*
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* Information about this chipset gathered from a released Intel Linux driver,
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* which was clearly a port of an NT driver.
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*/
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/*
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* Various Descriptor Structures.
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* These are all in little endian format (for now).
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*/
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typedef struct {
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u_int32_t lowpart;
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u_int32_t highpart;
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} wxpa_t, wxrp_t;
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/*
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* Receive Descriptor.
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* The base address of a receive descriptor ring must be on a 4KB boundary,
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* and they must be allocated in multiples of 8.
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*/
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typedef struct {
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wxpa_t address; /* physical address of buffer */
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u_int16_t length;
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u_int16_t csum;
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u_int8_t status;
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u_int8_t errors;
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u_int16_t special;
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} wxrd_t;
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#define RDSTAT_DD 0x1 /* descriptor done */
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#define RDSTAT_EOP 0x2 /* end of packet */
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#define RDSTAT_RSVD 0x74 /* reserved bits */
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#define RDERR_CRC 0x1 /* CRC Error */
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#define RDERR_SE 0x2 /* Symbol Error */
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#define RDERR_SEQ 0x4 /* Sequence Error */
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/*
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* Transmit Descriptor
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* The base address of a transmit descriptor ring must be on a 4KB boundary,
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* and they must be allocated in multiples of 8.
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*/
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typedef struct {
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wxpa_t address;
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u_int16_t length;
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u_int8_t cso; /* checksum offset */
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u_int8_t cmd; /* cmd */
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u_int8_t status; /* status */
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u_int8_t css; /* checksum start */
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u_int16_t special;
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} wxtd_t;
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#define TXCMD_EOP 0x1 /* last packet */
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#define TXCMD_IFCS 0x2 /* insert FCS */
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#define TXCMD_IC 0x4 /* insert checksum */
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#define TXCMD_RS 0x8 /* report status */
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#define TXCMD_RPS 0x10 /* report packet sent */
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#define TXCMD_SM 0x20 /* symbol mode */
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#define TXCMD_IDE 0x80 /* interrupt delay enable */
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#define TXSTS_DD 0x1 /* descriptor done */
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#define TXSTS_EC 0x2 /* excess collisions */
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#define TXSTS_LC 0x4 /* late collision */
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/*
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* This device can only be accessed via memory space.
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*/
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/*
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* Register access via offsets.
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*/
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#define WXREG_DCR 0x00000000
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#define WXREG_DSR 0x00000008
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#define WXREG_EECDR 0x00000010
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#define WXREG_FCAL 0x00000028
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#define WXREG_FCAH 0x0000002C
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#define WXREG_FCT 0x00000030
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#define WXREG_VET 0x00000038
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#define WXREG_RAL_BASE 0x00000040
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#define WXREG_RAL_LO(x) (WXREG_RAL_BASE + ((x) << 3))
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#define WXREG_RAL_HI(x) (WXREG_RAL_LO(x) + 4)
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#define WXREG_ICR 0x000000c0
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#define WXREG_ICS 0x000000c8
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#define WXREG_IMASK 0x000000d0
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#define WXREG_IMCLR 0x000000d8
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#define WXREG_RCTL 0x00000100
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#define WXREG_RDTR0 0x00000108
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#define WXREG_RDBA0_LO 0x00000110
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#define WXREG_RDBA0_HI 0x00000114
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#define WXREG_RDLEN0 0x00000118
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#define WXREG_RDH0 0x00000120
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#define WXREG_RDT0 0x00000128
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#define WXREG_RDTR1 0x00000130
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#define WXREG_RDBA1_LO 0x00000138
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#define WXREG_RDBA1_HI 0x0000013C
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#define WXREG_RDLEN1 0x00000140
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#define WXREG_RDH1 0x00000148
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#define WXREG_RDT1 0x00000150
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#define WXREG_FLOW_RCV_HI 0x00000160
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#define WXREG_FLOW_RCV_LO 0x00000168
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#define WXREG_FLOW_XTIMER 0x00000170
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#define WXREG_XMIT_CFGW 0x00000178
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#define WXREG_RECV_CFGW 0x00000180
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#define WXREG_MTA 0x00000200
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#define WXREG_TCTL 0x00000400
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#define WXREG_TQSA_LO 0x00000408
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#define WXREG_TQSA_HI 0x0000040C
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#define WXREG_TIPG 0x00000410
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#define WXREG_TQC 0x00000418
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#define WXREG_TDBA_LO 0x00000420
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#define WXREG_TDBA_HI 0x00000424
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#define WXREG_TDLEN 0x00000428
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#define WXREG_TDH 0x00000430
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#define WXREG_TDT 0x00000438
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#define WXREG_TIDV 0x00000440
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#define WXREG_VFTA 0x00000600
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#define WX_RAL_TAB_SIZE 16
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#define WX_RAL_AV 0x80000000
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#define WX_MC_TAB_SIZE 128
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#define WX_VLAN_TAB_SIZE 128
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/*
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* Device Control Register Defines
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*/
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#define WXDCR_FD 0x1 /* full duplex */
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#define WXDCR_BEM 0x2 /* big endian mode */
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#define WXDCR_FAIR 0x4 /* 1->Fairness, 0->Receive Priority */
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#define WXDCR_LRST 0x8 /* Link Reset */
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#define WXDCR_SLU 0x40 /* Set Link Up */
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#define WXDCR_ILOS 0x80 /* Invert Loss-of-Signal */
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#define WXDCR_SWDPINS_SHIFT 18
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#define WXDCR_SWDPINS_MASK 0xf
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#define WXDCR_SWDPIN0 (1 << 18)
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#define WXDCR_SWDPIN1 (1 << 19)
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#define WXDCR_SWDPIN2 (1 << 20)
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#define WXDCR_SWDPIN3 (1 << 21)
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#define WXDCR_SWDPIO_SHIFT 22
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#define WXDCR_SWDPIO_MASK 0xf
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#define WXDCR_SWDPIO0 (1 << 22)
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#define WXDCR_SWDPIO1 (1 << 23)
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#define WXDCR_SWDPIO2 (1 << 24)
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#define WXDCR_SWDPIO3 (1 << 25)
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#define WXDCR_RST 0x04000000 /* Device Reset (self clearing) */
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#define WXDCR_RFCE 0x08000000 /* Receive Flow Control Enable */
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#define WXDCR_TFCE 0x10000000 /* Transmit Flow Control Enable */
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#define WXDCR_RTE 0x20000000 /* Routing Tag Enable */
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#define WXDCR_VME 0x40000000 /* VLAN Mode Enable */
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/*
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* Device Status Register Defines
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*/
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#define WXDSR_FD 0x1 /* full duplex */
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#define WXDSR_LU 0x2 /* link up */
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#define WXDSR_TXCLK 0x4 /* transmit clock running */
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#define WXDSR_RBCLK 0x8 /* receive clock running */
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#define WXDSR_TXOFF 0x10 /* transmit paused */
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/*
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* EEPROM Register Defines
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*/
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#define WXEECD_SK 0x1 /* enable clock */
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#define WXEECD_CS 0x2 /* chip select */
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#define WXEECD_DI 0x4 /* data input */
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#define WXEECD_DO 0x8 /* data output */
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#define EEPROM_READ_OPCODE 0x6
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/*
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* Constant Flow Control Frame MAC Address and Type values.
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*/
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#define FC_FRM_CONST_LO 0x00C28001
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#define FC_FRM_CONST_HI 0x0100
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#define FC_TYP_CONST 0x8808
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/*
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* Bits pertinent for the Receive Address register pairs. The low address
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* is the low 32 bits of a 48 bit MAC address. The high address contains
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* bits 32-47 of the 48 bit MAC address. The top bit in the high address
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* is a 'valid' bit.
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*/
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#define WXRAH_RDR1 0x40000000 /* second receive descriptor ring */
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#define WXRAH_VALID 0x80000000
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/*
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* Interrupt Cause Bits
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*/
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#define WXISR_TXDW 0x1 /* transmit descriptor written back */
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#define WXISR_TXQE 0x2 /* transmit queue empty */
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#define WXISR_LSC 0x4 /* link status change */
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#define WXISR_RXSEQ 0x8 /* receive sequence error */
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#define WXISR_RXDMT0 0x10 /* receiver ring 0 getting empty */
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#define WXISR_RXO 0x40 /* receiver overrun */
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#define WXISR_RXT0 0x80 /* ring 0 receiver timer interrupt */
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#define WXISR_PCIE 0x200 /* ?? Probably PCI interface error... */
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#define WXIENABLE_DEFAULT \
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(WXISR_RXO|WXISR_RXT0|WXISR_RXDMT0|WXISR_RXSEQ|WXISR_LSC|WXISR_PCIE)
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#define WXDISABLE 0xffffffff
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/*
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* Receive Control Register bits.
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*/
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#define WXRCTL_RST 0x1 /* receiver reset */
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#define WXRCTL_EN 0x2 /* receiver enable */
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#define WXRCTL_SBP 0x4 /* store bad packets */
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#define WXRCTL_UPE 0x8 /* unicast promiscuos mode */
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#define WXRCTL_MPE 0x10 /* multicast promiscuous mode */
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#define WXRCTL_LPE 0x20 /* large packet enable */
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#define WXRCTL_BAM 0x8000 /* broadcast accept mode */
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#define WXRCTL_2KRBUF (0 << 16) /* 2-Kbyte Receive Buffers */
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#define WXRCTL_1KRBUF (1 << 16) /* 1-Kbyte Receive Buffers */
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#define WXRCTL_512BRBUF (2 << 16) /* 512 Byte Receive Buffers */
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#define WXRCTL_256BRBUF (3 << 16) /* 256 Byte Receive Buffers */
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/*
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* Receive Delay Timer Register bits.
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*/
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#define WXRDTR_FPD 0x80000000 /* flush partial descriptor */
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/*
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* Transmit Configuration Word defines
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*/
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#define WXTXCW_FD 0x00000020 /* Full Duplex */
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#define WXTXCW_PMASK 0x00000180 /* pause mask */
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#define WXTXCW_ANE 0x80000000 /* AutoNegotiate */
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#define WXTXCW_DEFAULT 0x800001A0
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/*
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* Transmit Control Register defines.
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*/
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#define WXTCTL_RST 0x1 /* transmitter reset */
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#define WXTCTL_EN 0x2 /* transmitter enable */
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#define WXTCTL_PSP 0x8 /* pad short packets */
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#define WXTCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - Collision Threshold */
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#define WXTCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - Collision Distance */
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#define WXTCTL_SWXOFF (1 << 22) /* Software XOFF */
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#define WX_COLLISION_THRESHOLD 15
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#define WX_FDX_COLLISION_DX 64
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#define WX_HDX_COLLISION_DX 512
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/*
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* Miscellaneous
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*/
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#define WX_EEPROM_MAC_OFF 0
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/*
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* Offset for Initialization Control Word #1
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*/
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#define WX_EEPROM_CTLR1_OFF 0xA
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#define WX_EEPROM_CTLR1_FD (1 << 10)
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#define WX_EEPROM_CTLR1_SWDPIO_SHIFT 5
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#define WX_EEPROM_CTLR1_ILOS (1 << 4)
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#define WX_XTIMER_DFLT 0x100
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#define WX_RCV_FLOW_HI_DFLT 0x8000
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#define WX_RCV_FLOW_LO_DFLT 0x4000
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#define WX_TIPG_DFLT (10 | (2 << 10) | (10 << 20))
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#define WX_CRC_LENGTH 4
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/*
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* Hardware cannot transmit less than 16 bytes. It also cannot
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* successfully receive less than 60 bytes.
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*/
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#define WX_MIN_XPKT_SIZE 16
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#define WX_MIN_RPKT_SIZE 60
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#define WX_MAX_PKT_SIZE 1514
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