326 lines
13 KiB
TableGen
326 lines
13 KiB
TableGen
//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction aliases for Sparc.
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//===----------------------------------------------------------------------===//
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// Instruction aliases for conditional moves.
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// mov<cond> <ccreg> rs2, rd
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multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
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Instruction movrr, Instruction movri,
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Instruction fmovs, Instruction fmovd> {
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// mov<cond> (%icc|%xcc), rs2, rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
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", $rs2, $rd"),
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(movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
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// mov<cond> (%icc|%xcc), simm11, rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
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", $simm11, $rd"),
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(movri IntRegs:$rd, i32imm:$simm11, condVal)>;
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// fmovs<cond> (%icc|%xcc), $rs2, $rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
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", $rs2, $rd"),
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(fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
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// fmovd<cond> (%icc|%xcc), $rs2, $rd
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def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
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", $rs2, $rd"),
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(fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
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}
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// mov<cond> <ccreg> rs2, rd
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multiclass fpcond_mov_alias<string cond, int condVal,
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Instruction movrr, Instruction movri,
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Instruction fmovs, Instruction fmovd> {
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// mov<cond> %fcc[0-3], rs2, rd
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def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
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(movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
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// mov<cond> %fcc[0-3], simm11, rd
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def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
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(movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
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// fmovs<cond> %fcc[0-3], $rs2, $rd
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def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
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(fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
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// fmovd<cond> %fcc[0-3], $rs2, $rd
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def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
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(fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
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}
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// Instruction aliases for integer conditional branches and moves.
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multiclass int_cond_alias<string cond, int condVal> {
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// b<cond> $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
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(BCOND brtarget:$imm, condVal)>;
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// b<cond>,a $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
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(BCONDA brtarget:$imm, condVal)>;
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// b<cond> %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
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(BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond>,pt %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),
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(BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond>,a %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),
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(BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond>,a,pt %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),
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(BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond>,pn %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),
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(BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond>,a,pn %icc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),
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(BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
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// b<cond> %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
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(BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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// b<cond>,pt %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),
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(BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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// b<cond>,a %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),
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(BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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// b<cond>,a,pt %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),
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(BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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// b<cond>,pn %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),
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(BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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// b<cond>,a,pn %xcc, $imm
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def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),
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(BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
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defm : intcond_mov_alias<cond, condVal, " %icc",
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MOVICCrr, MOVICCri,
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FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
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defm : intcond_mov_alias<cond, condVal, " %xcc",
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MOVXCCrr, MOVXCCri,
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FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
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// fmovq<cond> (%icc|%xcc), $rs2, $rd
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def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
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(FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
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Requires<[HasV9, HasHardQuad]>;
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def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
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(FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
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Requires<[Is64Bit, HasHardQuad]>;
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// t<cond> %icc, rs1 + rs2
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def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
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(TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %icc, rs => t<cond> %icc, G0 + rs
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def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"),
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(TICCrr G0, IntRegs:$rs2, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %xcc, rs1 + rs2
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def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
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(TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
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def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"),
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(TXCCrr G0, IntRegs:$rs2, condVal)>,
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Requires<[HasV9]>;
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// t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
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def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
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(TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
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// t<cond> rs=> t<cond> %icc, G0 + rs2
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def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"),
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(TICCrr G0, IntRegs:$rs2, condVal)>;
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// t<cond> %icc, rs1 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),
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(TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %icc, imm => t<cond> %icc, G0 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"),
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(TICCri G0, i32imm:$imm, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %xcc, rs1 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),
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(TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,
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Requires<[HasV9]>;
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// t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"),
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(TXCCri G0, i32imm:$imm, condVal)>,
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Requires<[HasV9]>;
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// t<cond> rs1 + imm => t<cond> %icc, rs1 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),
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(TICCri IntRegs:$rs1, i32imm:$imm, condVal)>;
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// t<cond> imm => t<cond> %icc, G0 + imm
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def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"),
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(TICCri G0, i32imm:$imm, condVal)>;
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}
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// Instruction aliases for floating point conditional branches and moves.
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multiclass fp_cond_alias<string cond, int condVal> {
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// fb<cond> $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
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(FBCOND brtarget:$imm, condVal), 0>;
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// fb<cond>,a $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
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(FBCONDA brtarget:$imm, condVal), 0>;
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// fb<cond> %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
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(BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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// fb<cond>,pt %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
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(BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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// fb<cond>,a %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
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(BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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// fb<cond>,a,pt %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
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(BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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// fb<cond>,pn %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
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(BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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// fb<cond>,a,pn %fcc0, $imm
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def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
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(BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>,
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Requires<[HasV9]>;
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defm : fpcond_mov_alias<cond, condVal,
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V9MOVFCCrr, V9MOVFCCri,
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V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
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// fmovq<cond> %fcc0, $rs2, $rd
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def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
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(V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
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condVal)>,
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Requires<[HasV9, HasHardQuad]>;
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}
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defm : int_cond_alias<"a", 0b1000>;
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defm : int_cond_alias<"n", 0b0000>;
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defm : int_cond_alias<"ne", 0b1001>;
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defm : int_cond_alias<"e", 0b0001>;
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defm : int_cond_alias<"g", 0b1010>;
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defm : int_cond_alias<"le", 0b0010>;
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defm : int_cond_alias<"ge", 0b1011>;
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defm : int_cond_alias<"l", 0b0011>;
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defm : int_cond_alias<"gu", 0b1100>;
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defm : int_cond_alias<"leu", 0b0100>;
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defm : int_cond_alias<"cc", 0b1101>;
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defm : int_cond_alias<"cs", 0b0101>;
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defm : int_cond_alias<"pos", 0b1110>;
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defm : int_cond_alias<"neg", 0b0110>;
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defm : int_cond_alias<"vc", 0b1111>;
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defm : int_cond_alias<"vs", 0b0111>;
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defm : fp_cond_alias<"a", 0b0000>;
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defm : fp_cond_alias<"n", 0b1000>;
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defm : fp_cond_alias<"u", 0b0111>;
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defm : fp_cond_alias<"g", 0b0110>;
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defm : fp_cond_alias<"ug", 0b0101>;
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defm : fp_cond_alias<"l", 0b0100>;
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defm : fp_cond_alias<"ul", 0b0011>;
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defm : fp_cond_alias<"lg", 0b0010>;
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defm : fp_cond_alias<"ne", 0b0001>;
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defm : fp_cond_alias<"e", 0b1001>;
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defm : fp_cond_alias<"ue", 0b1010>;
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defm : fp_cond_alias<"ge", 0b1011>;
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defm : fp_cond_alias<"uge", 0b1100>;
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defm : fp_cond_alias<"le", 0b1101>;
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defm : fp_cond_alias<"ule", 0b1110>;
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defm : fp_cond_alias<"o", 0b1111>;
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// Instruction aliases for JMPL.
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// jmp addr -> jmpl addr, %g0
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def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
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def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
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// call addr -> jmpl addr, %o7
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def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;
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def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;
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// retl -> RETL 8
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def : InstAlias<"retl", (RETL 8)>;
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// ret -> RET 8
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def : InstAlias<"ret", (RET 8)>;
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// mov reg, rd -> or %g0, reg, rd
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def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
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// mov simm13, rd -> or %g0, simm13, rd
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def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
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// restore -> restore %g0, %g0, %g0
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def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
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def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
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def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
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def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
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def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
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def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
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def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
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def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
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def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
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Requires<[HasHardQuad]>;
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def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
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def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
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DFPRegs:$rs2)>;
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def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
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QFPRegs:$rs2)>,
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Requires<[HasHardQuad]>;
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