1713e81b9c
providing the original driver, and thanks to IronSystems for providing hardware for testing.
430 lines
14 KiB
C
430 lines
14 KiB
C
/*
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* Copyright (c) 2003-2004 MARVELL SEMICONDUCTOR ISRAEL, LTD.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __INCmvSatah
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#define __INCmvSatah
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#ifndef SUPPORT_MV_SATA_GEN_1
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#define SUPPORT_MV_SATA_GEN_1 1
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#endif
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#ifndef SUPPORT_MV_SATA_GEN_2
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#define SUPPORT_MV_SATA_GEN_2 0
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#endif
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#if SUPPORT_MV_SATA_GEN_1==1 && SUPPORT_MV_SATA_GEN_2==1
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#define MV_SATA_GEN_1(x) ((x)->sataAdapterGeneration==1)
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#define MV_SATA_GEN_2(x) ((x)->sataAdapterGeneration==2)
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#elif SUPPORT_MV_SATA_GEN_1==1
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#define MV_SATA_GEN_1(x) 1
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#define MV_SATA_GEN_2(x) 0
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#elif SUPPORT_MV_SATA_GEN_2==1
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#define MV_SATA_GEN_1(x) 0
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#define MV_SATA_GEN_2(x) 1
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#else
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#error "Which IC do you support?"
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#endif
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/* Definitions */
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/* MV88SX50XX specific defines */
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#define MV_SATA_VENDOR_ID 0x11AB
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#define MV_SATA_DEVICE_ID_5080 0x5080
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#define MV_SATA_DEVICE_ID_5081 0x5081
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#define MV_SATA_DEVICE_ID_6080 0x6080
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#define MV_SATA_DEVICE_ID_6081 0x6081
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#define MV_SATA_CHANNELS_NUM 8
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#define MV_SATA_UNITS_NUM 2
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#define MV_SATA_PCI_BAR0_SPACE_SIZE (1<<18) /* 256 Kb*/
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#define CHANNEL_QUEUE_LENGTH 32
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#define CHANNEL_QUEUE_MASK 0x1F
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#define MV_EDMA_QUEUE_LENGTH 32 /* Up to 32 outstanding */
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/* commands per SATA channel*/
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#define MV_EDMA_QUEUE_MASK 0x1F
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#define MV_EDMA_REQUEST_QUEUE_SIZE 1024 /* 32*32 = 1KBytes */
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#define MV_EDMA_RESPONSE_QUEUE_SIZE 256 /* 32*8 = 256 Bytes */
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#define MV_EDMA_REQUEST_ENTRY_SIZE 32
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#define MV_EDMA_RESPONSE_ENTRY_SIZE 8
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#define MV_EDMA_PRD_ENTRY_SIZE 16 /* 16Bytes*/
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#define MV_EDMA_PRD_NO_SNOOP_FLAG 0x00000001 /* MV_BIT0 */
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#define MV_EDMA_PRD_EOT_FLAG 0x00008000 /* MV_BIT15 */
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#define MV_ATA_IDENTIFY_DEV_DATA_LENGTH 256 /* number of words(2 byte)*/
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#define MV_ATA_MODEL_NUMBER_LEN 40
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#define ATA_SECTOR_SIZE 512
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/* Log messages level defines */
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#define MV_DEBUG 0x1
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#define MV_DEBUG_INIT 0x2
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#define MV_DEBUG_INTERRUPTS 0x4
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#define MV_DEBUG_SATA_LINK 0x8
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#define MV_DEBUG_UDMA_COMMAND 0x10
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#define MV_DEBUG_NON_UDMA_COMMAND 0x20
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#define MV_DEBUG_ERROR 0x40
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/* Typedefs */
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typedef enum mvUdmaType
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{
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MV_UDMA_TYPE_READ, MV_UDMA_TYPE_WRITE
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} MV_UDMA_TYPE;
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typedef enum mvFlushType
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{
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MV_FLUSH_TYPE_CALLBACK, MV_FLUSH_TYPE_NONE
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} MV_FLUSH_TYPE;
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typedef enum mvCompletionType
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{
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MV_COMPLETION_TYPE_NORMAL, MV_COMPLETION_TYPE_ERROR,
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MV_COMPLETION_TYPE_ABORT
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} MV_COMPLETION_TYPE;
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typedef enum mvEventType
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{
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MV_EVENT_TYPE_ADAPTER_ERROR, MV_EVENT_TYPE_SATA_CABLE
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} MV_EVENT_TYPE;
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typedef enum mvEdmaMode
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{
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MV_EDMA_MODE_QUEUED,
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MV_EDMA_MODE_NOT_QUEUED,
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MV_EDMA_MODE_NATIVE_QUEUING
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} MV_EDMA_MODE;
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typedef enum mvEdmaQueueResult
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{
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MV_EDMA_QUEUE_RESULT_OK = 0,
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MV_EDMA_QUEUE_RESULT_EDMA_DISABLED,
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MV_EDMA_QUEUE_RESULT_FULL,
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MV_EDMA_QUEUE_RESULT_BAD_LBA_ADDRESS,
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MV_EDMA_QUEUE_RESULT_BAD_PARAMS
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} MV_EDMA_QUEUE_RESULT;
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typedef enum mvQueueCommandResult
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{
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MV_QUEUE_COMMAND_RESULT_OK = 0,
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MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED,
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MV_QUEUE_COMMAND_RESULT_FULL,
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MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS,
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MV_QUEUE_COMMAND_RESULT_BAD_PARAMS
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} MV_QUEUE_COMMAND_RESULT;
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typedef enum mvNonUdmaProtocol
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{
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MV_NON_UDMA_PROTOCOL_NON_DATA,
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MV_NON_UDMA_PROTOCOL_PIO_DATA_IN,
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MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT
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} MV_NON_UDMA_PROTOCOL;
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struct mvDmaRequestQueueEntry;
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struct mvDmaResponseQueueEntry;
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struct mvDmaCommandEntry;
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struct mvSataAdapter;
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struct mvStorageDevRegisters;
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typedef MV_BOOLEAN (* HPTLIBAPI mvSataCommandCompletionCallBack_t)(struct mvSataAdapter *,
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MV_U8,
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MV_COMPLETION_TYPE,
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MV_VOID_PTR, MV_U16,
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MV_U32,
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struct mvStorageDevRegisters FAR*);
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typedef enum mvQueuedCommandType
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{
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MV_QUEUED_COMMAND_TYPE_UDMA,
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MV_QUEUED_COMMAND_TYPE_NONE_UDMA
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} MV_QUEUED_COMMAND_TYPE;
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typedef struct mvUdmaCommandParams
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{
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MV_UDMA_TYPE readWrite;
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MV_BOOLEAN isEXT;
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MV_U32 lowLBAAddress;
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MV_U16 highLBAAddress;
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MV_U16 numOfSectors;
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MV_U32 prdLowAddr;
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MV_U32 prdHighAddr;
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mvSataCommandCompletionCallBack_t callBack;
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MV_VOID_PTR commandId;
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} MV_UDMA_COMMAND_PARAMS;
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typedef struct mvNoneUdmaCommandParams
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{
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MV_NON_UDMA_PROTOCOL protocolType;
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MV_BOOLEAN isEXT;
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MV_U16_PTR bufPtr;
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MV_U32 count;
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MV_U16 features;
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MV_U16 sectorCount;
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MV_U16 lbaLow;
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MV_U16 lbaMid;
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MV_U16 lbaHigh;
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MV_U8 device;
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MV_U8 command;
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mvSataCommandCompletionCallBack_t callBack;
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MV_VOID_PTR commandId;
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} MV_NONE_UDMA_COMMAND_PARAMS;
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typedef struct mvQueueCommandInfo
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{
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MV_QUEUED_COMMAND_TYPE type;
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union
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{
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MV_UDMA_COMMAND_PARAMS udmaCommand;
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MV_NONE_UDMA_COMMAND_PARAMS NoneUdmaCommand;
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} commandParams;
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} MV_QUEUE_COMMAND_INFO;
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/* The following structure is for the Core Driver internal usage */
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typedef struct mvQueuedCommandEntry
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{
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MV_BOOLEAN isFreeEntry;
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MV_U8 commandTag;
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struct mvQueuedCommandEntry *next;
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struct mvQueuedCommandEntry *prev;
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MV_QUEUE_COMMAND_INFO commandInfo;
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} MV_QUEUED_COMMAND_ENTRY;
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/* The following structures are part of the Core Driver API */
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typedef struct mvSataChannel
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{
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/* Fields set by Intermediate Application Layer */
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MV_U8 channelNumber;
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MV_BOOLEAN waitingForInterrupt;
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MV_BOOLEAN lba48Address;
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MV_BOOLEAN maxReadTransfer;
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struct mvDmaRequestQueueEntry FAR *requestQueue;
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struct mvDmaResponseQueueEntry FAR *responseQueue;
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MV_U32 requestQueuePciHiAddress;
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MV_U32 requestQueuePciLowAddress;
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MV_U32 responseQueuePciHiAddress;
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MV_U32 responseQueuePciLowAddress;
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/* Fields set by CORE driver */
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struct mvSataAdapter *mvSataAdapter;
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MV_OS_SEMAPHORE semaphore;
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MV_U32 eDmaRegsOffset;
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MV_U16 identifyDevice[MV_ATA_IDENTIFY_DEV_DATA_LENGTH];
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MV_BOOLEAN EdmaActive;
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MV_EDMA_MODE queuedDMA;
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MV_U8 outstandingCommands;
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MV_BOOLEAN workAroundDone;
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struct mvQueuedCommandEntry commandsQueue[CHANNEL_QUEUE_LENGTH];
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struct mvQueuedCommandEntry *commandsQueueHead;
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struct mvQueuedCommandEntry *commandsQueueTail;
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MV_BOOLEAN queueCommandsEnabled;
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MV_U8 noneUdmaOutstandingCommands;
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MV_U8 EdmaQueuedCommands;
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MV_U32 freeIDsStack[MV_EDMA_QUEUE_LENGTH];
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MV_U32 freeIDsNum;
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MV_U32 reqInPtr;
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MV_U32 rspOutPtr;
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} MV_SATA_CHANNEL;
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typedef struct mvSataAdapter
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{
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/* Fields set by Intermediate Application Layer */
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MV_U32 adapterId;
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MV_U8 pcbVersion;
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MV_U8 pciConfigRevisionId;
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MV_U16 pciConfigDeviceId;
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MV_VOID_PTR IALData;
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MV_BUS_ADDR_T adapterIoBaseAddress;
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MV_U32 intCoalThre[MV_SATA_UNITS_NUM];
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MV_U32 intTimeThre[MV_SATA_UNITS_NUM];
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MV_BOOLEAN (* HPTLIBAPI mvSataEventNotify)(struct mvSataAdapter *,
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MV_EVENT_TYPE,
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MV_U32, MV_U32);
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MV_SATA_CHANNEL *sataChannel[MV_SATA_CHANNELS_NUM];
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MV_U32 pciCommand;
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MV_U32 pciSerrMask;
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MV_U32 pciInterruptMask;
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/* Fields set by CORE driver */
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MV_OS_SEMAPHORE semaphore;
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MV_U32 mainMask;
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MV_OS_SEMAPHORE interruptsMaskSem;
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MV_BOOLEAN implementA0Workarounds;
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MV_BOOLEAN implement50XXB0Workarounds;
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MV_BOOLEAN implement50XXB1Workarounds;
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MV_BOOLEAN implement50XXB2Workarounds;
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MV_BOOLEAN implement60X1A0Workarounds;
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MV_BOOLEAN implement60X1A1Workarounds;
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MV_BOOLEAN implement60X1B0Workarounds;
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MV_U8 sataAdapterGeneration;
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MV_U8 failLEDMask;
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MV_U8 signalAmps[MV_SATA_CHANNELS_NUM];
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MV_U8 pre[MV_SATA_CHANNELS_NUM];
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MV_BOOLEAN staggaredSpinup[MV_SATA_CHANNELS_NUM]; /* For 60x1 only */
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} MV_SATA_ADAPTER;
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typedef struct mvSataAdapterStatus
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{
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/* Fields set by CORE driver */
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MV_BOOLEAN channelConnected[MV_SATA_CHANNELS_NUM];
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MV_U32 pciDLLStatusAndControlRegister;
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MV_U32 pciCommandRegister;
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MV_U32 pciModeRegister;
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MV_U32 pciSERRMaskRegister;
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MV_U32 intCoalThre[MV_SATA_UNITS_NUM];
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MV_U32 intTimeThre[MV_SATA_UNITS_NUM];
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MV_U32 R00StatusBridgePortRegister[MV_SATA_CHANNELS_NUM];
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}MV_SATA_ADAPTER_STATUS;
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typedef struct mvSataChannelStatus
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{
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/* Fields set by CORE driver */
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MV_BOOLEAN isConnected;
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MV_U8 modelNumber[MV_ATA_MODEL_NUMBER_LEN];
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MV_BOOLEAN DMAEnabled;
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MV_EDMA_MODE queuedDMA;
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MV_U8 outstandingCommands;
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MV_U32 EdmaConfigurationRegister;
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MV_U32 EdmaRequestQueueBaseAddressHighRegister;
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MV_U32 EdmaRequestQueueInPointerRegister;
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MV_U32 EdmaRequestQueueOutPointerRegister;
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MV_U32 EdmaResponseQueueBaseAddressHighRegister;
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MV_U32 EdmaResponseQueueInPointerRegister;
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MV_U32 EdmaResponseQueueOutPointerRegister;
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MV_U32 EdmaCommandRegister;
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MV_U32 PHYModeRegister;
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}MV_SATA_CHANNEL_STATUS;
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/* this structure used by the IAL defines the PRD entries used by the EDMA HW */
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typedef struct mvSataEdmaPRDEntry
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{
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volatile MV_U32 lowBaseAddr;
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volatile MV_U16 byteCount;
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volatile MV_U16 flags;
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volatile MV_U32 highBaseAddr;
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volatile MV_U32 reserved;
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}MV_SATA_EDMA_PRD_ENTRY;
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/* API Functions */
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/* CORE driver Adapter Management */
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MV_BOOLEAN HPTLIBAPI mvSataInitAdapter(MV_SATA_ADAPTER *pAdapter);
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MV_BOOLEAN HPTLIBAPI mvSataShutdownAdapter(MV_SATA_ADAPTER *pAdapter);
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MV_BOOLEAN HPTLIBAPI mvSataGetAdapterStatus(MV_SATA_ADAPTER *pAdapter,
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MV_SATA_ADAPTER_STATUS *pAdapterStatus);
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MV_U32 HPTLIBAPI mvSataReadReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset);
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MV_VOID HPTLIBAPI mvSataWriteReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset,
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MV_U32 regValue);
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MV_VOID HPTLIBAPI mvEnableAutoFlush(MV_VOID);
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MV_VOID HPTLIBAPI mvDisableAutoFlush(MV_VOID);
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/* CORE driver SATA Channel Management */
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MV_BOOLEAN HPTLIBAPI mvSataConfigureChannel(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvSataRemoveChannel(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvSataIsStorageDeviceConnected(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvSataChannelHardReset(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvSataConfigEdmaMode(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex,
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MV_EDMA_MODE eDmaMode, MV_U8 maxQueueDepth);
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MV_BOOLEAN HPTLIBAPI mvSataEnableChannelDma(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvSataDisableChannelDma(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvSataFlushDmaQueue(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex,
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MV_FLUSH_TYPE flushType);
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MV_U8 HPTLIBAPI mvSataNumOfDmaCommands(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvSataSetIntCoalParams (MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit,
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MV_U32 intCoalThre, MV_U32 intTimeThre);
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MV_BOOLEAN HPTLIBAPI mvSataSetChannelPhyParams(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex,
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MV_U8 signalAmps, MV_U8 pre);
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MV_BOOLEAN HPTLIBAPI mvSataChannelPhyShutdown(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvSataChannelPhyPowerOn(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex);
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MV_BOOLEAN HPTLIBAPI mvSataChannelSetEdmaLoopBackMode(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex,
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MV_BOOLEAN loopBackOn);
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MV_BOOLEAN HPTLIBAPI mvSataGetChannelStatus(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex,
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MV_SATA_CHANNEL_STATUS *pChannelStatus);
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/* Execute UDMA ATA commands */
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MV_EDMA_QUEUE_RESULT HPTLIBAPI mvSataQueueUDmaCommand(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex,
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MV_UDMA_TYPE readWrite,
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MV_U32 lowLBAAddr,
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MV_U16 highLBAAddr,
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MV_U16 sectorCount,
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MV_U32 prdLowAddr,
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MV_U32 prdHighAddr,
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mvSataCommandCompletionCallBack_t callBack,
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MV_VOID_PTR commandId);
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MV_QUEUE_COMMAND_RESULT HPTLIBAPI mvSataQueueCommand(MV_SATA_ADAPTER *pAdapter,
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MV_U8 channelIndex,
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MV_QUEUE_COMMAND_INFO FAR *pCommandParams);
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/* Interrupt Service Routine */
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MV_BOOLEAN HPTLIBAPI mvSataInterruptServiceRoutine(MV_SATA_ADAPTER *pAdapter);
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MV_BOOLEAN HPTLIBAPI mvSataMaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter);
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MV_BOOLEAN HPTLIBAPI mvSataUnmaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter);
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/* Command Completion and Event Notification (user implemented) */
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MV_BOOLEAN HPTLIBAPI mvSataEventNotify(MV_SATA_ADAPTER *, MV_EVENT_TYPE ,
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MV_U32, MV_U32);
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/*
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* Staggered spin-ip support and SATA interface speed control
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* (relevant for 60x1 adapters)
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*/
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MV_BOOLEAN HPTLIBAPI mvSataEnableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter);
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MV_BOOLEAN HPTLIBAPI mvSataDisableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter);
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#endif
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