dac91f5998
generator, found on IvyBridge and supposedly later CPUs, accessible with RDRAND instruction. From the Intel whitepapers and articles about Bull Mountain, it seems that we do not need to perform post-processing of RDRAND results, like AES-encryption of the data with random IV and keys, which was done for Padlock. Intel claims that sanitization is performed in hardware. Make both Padlock and Bull Mountain random generators support code covered by kernel config options, for the benefit of people who prefer minimal kernels. Also add the tunables to disable hardware generator even if detected. Reviewed by: markm, secteam (simon) Tested by: bapt, Michael Moll <kvedulv@kvedulv.de> MFC after: 3 weeks
212 lines
5.3 KiB
C
212 lines
5.3 KiB
C
/*-
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* Copyright (c) 2004 Mark R V Murray
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer
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* in this position and unchanged.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cpu.h"
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#ifdef PADLOCK_RNG
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#include <sys/param.h>
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#include <sys/time.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/selinfo.h>
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#include <sys/systm.h>
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#include <machine/pcb.h>
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#include <dev/random/randomdev.h>
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#define RANDOM_BLOCK_SIZE 256
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#define CIPHER_BLOCK_SIZE 16
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static void random_nehemiah_init(void);
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static void random_nehemiah_deinit(void);
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static int random_nehemiah_read(void *, int);
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struct random_systat random_nehemiah = {
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.ident = "Hardware, VIA Nehemiah",
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.init = random_nehemiah_init,
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.deinit = random_nehemiah_deinit,
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.read = random_nehemiah_read,
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.write = (random_write_func_t *)random_null_func,
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.reseed = (random_reseed_func_t *)random_null_func,
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.seeded = 1,
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};
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union VIA_ACE_CW {
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uint64_t raw;
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struct {
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u_int round_count : 4;
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u_int algorithm_type : 3;
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u_int key_generation_type : 1;
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u_int intermediate : 1;
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u_int decrypt : 1;
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u_int key_size : 2;
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u_int filler0 : 20;
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u_int filler1 : 32;
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u_int filler2 : 32;
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u_int filler3 : 32;
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} field;
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};
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/* The extra 7 is to allow an 8-byte write on the last byte of the
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* arrays. The ACE wants the AES data 16-byte/128-bit aligned, and
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* it _always_ writes n*64 bits. The RNG does not care about alignment,
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* and it always writes n*32 bits or n*64 bits.
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*/
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static uint8_t key[CIPHER_BLOCK_SIZE+7] __aligned(16);
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static uint8_t iv[CIPHER_BLOCK_SIZE+7] __aligned(16);
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static uint8_t in[RANDOM_BLOCK_SIZE+7] __aligned(16);
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static uint8_t out[RANDOM_BLOCK_SIZE+7] __aligned(16);
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static union VIA_ACE_CW acw __aligned(16);
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static struct fpu_kern_ctx *fpu_ctx_save;
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static struct mtx random_nehemiah_mtx;
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/* ARGSUSED */
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static __inline size_t
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VIA_RNG_store(void *buf)
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{
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#ifdef __GNUCLIKE_ASM
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uint32_t retval = 0;
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uint32_t rate = 0;
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/* The .byte line is really VIA C3 "xstore" instruction */
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__asm __volatile(
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"movl $0,%%edx \n\t"
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".byte 0x0f, 0xa7, 0xc0"
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: "=a" (retval), "+d" (rate), "+D" (buf)
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:
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: "memory"
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);
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if (rate == 0)
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return (retval&0x1f);
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#endif
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return (0);
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}
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/* ARGSUSED */
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static __inline void
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VIA_ACE_cbc(void *in, void *out, size_t count, void *key, union VIA_ACE_CW *cw, void *iv)
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{
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#ifdef __GNUCLIKE_ASM
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/* The .byte line is really VIA C3 "xcrypt-cbc" instruction */
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__asm __volatile(
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"pushf \n\t"
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"popf \n\t"
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"rep \n\t"
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".byte 0x0f, 0xa7, 0xc8"
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: "+a" (iv), "+c" (count), "+D" (out), "+S" (in)
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: "b" (key), "d" (cw)
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: "cc", "memory"
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);
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#endif
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}
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static void
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random_nehemiah_init(void)
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{
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acw.raw = 0ULL;
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acw.field.round_count = 12;
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mtx_init(&random_nehemiah_mtx, "random nehemiah", NULL, MTX_DEF);
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fpu_ctx_save = fpu_kern_alloc_ctx(FPU_KERN_NORMAL);
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}
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void
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random_nehemiah_deinit(void)
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{
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fpu_kern_free_ctx(fpu_ctx_save);
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mtx_destroy(&random_nehemiah_mtx);
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}
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static int
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random_nehemiah_read(void *buf, int c)
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{
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int i, error;
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size_t count, ret;
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uint8_t *p;
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mtx_lock(&random_nehemiah_mtx);
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error = fpu_kern_enter(curthread, fpu_ctx_save, FPU_KERN_NORMAL);
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if (error != 0) {
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mtx_unlock(&random_nehemiah_mtx);
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return (0);
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}
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/* Get a random AES key */
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count = 0;
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p = key;
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do {
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ret = VIA_RNG_store(p);
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p += ret;
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count += ret;
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} while (count < CIPHER_BLOCK_SIZE);
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/* Get a random AES IV */
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count = 0;
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p = iv;
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do {
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ret = VIA_RNG_store(p);
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p += ret;
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count += ret;
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} while (count < CIPHER_BLOCK_SIZE);
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/* Get a block of random bytes */
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count = 0;
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p = in;
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do {
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ret = VIA_RNG_store(p);
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p += ret;
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count += ret;
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} while (count < RANDOM_BLOCK_SIZE);
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/* This is a Davies-Meyer hash of the most paranoid variety; the
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* key, IV and the data are all read directly from the hardware RNG.
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* All of these are used precisely once.
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*/
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VIA_ACE_cbc(in, out, RANDOM_BLOCK_SIZE/CIPHER_BLOCK_SIZE,
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key, &acw, iv);
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for (i = 0; i < RANDOM_BLOCK_SIZE; i++)
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out[i] ^= in[i];
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c = MIN(RANDOM_BLOCK_SIZE, c);
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memcpy(buf, out, (size_t)c);
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fpu_kern_leave(curthread, fpu_ctx_save);
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mtx_unlock(&random_nehemiah_mtx);
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return (c);
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}
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#endif
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