br f2d066e3f7 Add 64 byte linesize cache flushing routines for L1 instruction, L1 data ...

and L2 data caches.

Sponsored by:	HEIF5

2015-03-26 14:51:24 +00:00

..

adm5120

In order to reduce use of M_EXT outside of the mbuf allocator and

2015-01-06 12:59:37 +00:00

alchemy

Fix a typo introduced in r257338.

2013-10-31 02:27:16 +00:00

atheros

Add GPIO function mux configuration for AR934x SoCs.

2015-03-21 06:08:35 +00:00

beri

Correct the end address of the memory regions.

2014-12-19 12:09:29 +00:00

cavium

Implement GPIO_GET_BUS() method for all GPIO drivers.

2015-01-31 19:32:14 +00:00

conf

Remove duplicate AH_DEBUG_ALQ option.

2015-03-26 12:58:30 +00:00

gxemul

Add 32-bit support for Gxemul's oldtestmips machine emulation

2013-09-04 20:34:36 +00:00

idt

Mechanically convert to if_inc_counter().

2014-09-19 09:19:49 +00:00

include

Add 64 byte linesize cache flushing routines for L1 instruction, L1 data

2015-03-26 14:51:24 +00:00

malta

Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this

2013-11-30 22:17:27 +00:00

mips

Add 64 byte linesize cache flushing routines for L1 instruction, L1 data

2015-03-26 14:51:24 +00:00

nlm

Use sbuf_printf() for sysctl strings instead of static buffers and snprintf.

2015-03-14 23:30:03 +00:00

rmi

Use sbuf_printf() for sysctl strings instead of static buffers and snprintf.

2015-03-14 23:30:03 +00:00

rt305x

Implement GPIO_GET_BUS() method for all GPIO drivers.

2015-01-31 19:32:14 +00:00

sentry5

…

sibyte

Devices that rely on hints or identify routines for discovery need to

2013-10-29 14:07:31 +00:00