6e7bc5b60d
controller hardware most likely present on UHCI chipsets aswell. The bug manifests itself when issuing isochronous transfers and bulk transfers towards the same device simultaneously. From time to time it happens that either the completion IRQ was missing or that the completion IRQ was happening before the ITD/SITD was completely written back to memory. The workaround assumes that double buffered isochronous transfers are used, and that a second interrupt is generated at the beginning of the next isochronous transfer to complete the previous one. Possibly skipping the interrupt at the last isochronous frame is possible, but will then break single buffered isochronous transfers. For now we can live with some extra interrupts. MFC after: 1 week |
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at91dci_atmelarm.c | ||
at91dci.c | ||
at91dci.h | ||
atmegadci_atmelarm.c | ||
atmegadci.c | ||
atmegadci.h | ||
avr32dci.c | ||
avr32dci.h | ||
dwc_otg_atmelarm.c | ||
dwc_otg.c | ||
dwc_otg.h | ||
dwc_otgreg.h | ||
ehci_fsl.c | ||
ehci_imx.c | ||
ehci_ixp4xx.c | ||
ehci_mv.c | ||
ehci_pci.c | ||
ehci.c | ||
ehci.h | ||
ehcireg.h | ||
musb_otg_atmelarm.c | ||
musb_otg.c | ||
musb_otg.h | ||
ohci_atmelarm.c | ||
ohci_pci.c | ||
ohci_s3c24x0.c | ||
ohci.c | ||
ohci.h | ||
ohcireg.h | ||
uhci_pci.c | ||
uhci.c | ||
uhci.h | ||
uhcireg.h | ||
usb_controller.c | ||
uss820dci_atmelarm.c | ||
uss820dci.c | ||
uss820dci.h | ||
xhci_pci.c | ||
xhci.c | ||
xhci.h | ||
xhcireg.h |