536 lines
17 KiB
C
536 lines
17 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
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* Copyright (c) 2004-05 Vinod Kashyap
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* AMCC'S 3ware driver for 9000 series storage controllers.
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*
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* Author: Vinod Kashyap
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* Modifications by: Adam Radford
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* Modifications by: Manjunath Ranganathaiah
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*/
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#ifndef TW_CL_SHARE_H
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#define TW_CL_SHARE_H
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/*
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* Macros, structures and functions shared between OSL and CL,
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* and defined by CL.
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*/
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#define TW_CL_NULL ((TW_VOID *)0)
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#define TW_CL_TRUE 1
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#define TW_CL_FALSE 0
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#define TW_CL_VENDOR_ID 0x13C1 /* 3ware vendor id */
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#define TW_CL_DEVICE_ID_9K 0x1002 /* 9000 PCI series device id */
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#define TW_CL_DEVICE_ID_9K_X 0x1003 /* 9000 PCI-X series device id */
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#define TW_CL_DEVICE_ID_9K_E 0x1004 /* 9000 PCIe series device id */
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#define TW_CL_DEVICE_ID_9K_SA 0x1005 /* 9000 PCIe SAS series device id */
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#define TW_CL_BAR_TYPE_IO 1 /* I/O base address */
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#define TW_CL_BAR_TYPE_MEM 2 /* memory base address */
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#define TW_CL_BAR_TYPE_SBUF 3 /* SBUF base address */
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#ifdef TW_OSL_ENCLOSURE_SUPPORT
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#define TW_CL_MAX_NUM_UNITS 65 /* max # of units we support
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-- enclosure target id is 64 */
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#else /* TW_OSL_ENCLOSURE_SUPPORT */
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#define TW_CL_MAX_NUM_UNITS 32 /* max # of units we support */
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#endif /* TW_OSL_ENCLOSURE_SUPPORT */
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#define TW_CL_MAX_NUM_LUNS 255 /* max # of LUN's we support */
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#define TW_CL_MAX_IO_SIZE 0x20000 /* 128K */
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/*
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* Though we can support 256 simultaneous requests, we advertise as capable
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* of supporting only 255, since we want to keep one CL internal request
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* context packet always available for internal requests.
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*/
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#define TW_CL_MAX_SIMULTANEOUS_REQUESTS 256 /* max simult reqs supported */
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#define TW_CL_MAX_32BIT_SG_ELEMENTS 109 /* max 32-bit sg elements */
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#define TW_CL_MAX_64BIT_SG_ELEMENTS 72 /* max 64-bit sg elements */
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/* Possible values of ctlr->flags */
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#define TW_CL_64BIT_ADDRESSES (1<<0) /* 64 bit cmdpkt & SG addresses */
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#define TW_CL_64BIT_SG_LENGTH (1<<1) /* 64 bit SG length */
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#define TW_CL_START_CTLR_ONLY (1<<2) /* Start ctlr only */
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#define TW_CL_STOP_CTLR_ONLY (1<<3) /* Stop ctlr only */
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#define TW_CL_DEFERRED_INTR_USED (1<<5) /* OS Layer uses deferred intr */
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/* Possible error values from the Common Layer. */
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#define TW_CL_ERR_REQ_SUCCESS 0
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#define TW_CL_ERR_REQ_GENERAL_FAILURE (1<<0)
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#define TW_CL_ERR_REQ_INVALID_TARGET (1<<1)
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#define TW_CL_ERR_REQ_INVALID_LUN (1<<2)
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#define TW_CL_ERR_REQ_SCSI_ERROR (1<<3)
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#define TW_CL_ERR_REQ_AUTO_SENSE_VALID (1<<4)
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#define TW_CL_ERR_REQ_BUS_RESET (1<<5)
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#define TW_CL_ERR_REQ_UNABLE_TO_SUBMIT_COMMAND (1<<6)
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/* Possible values of req_pkt->flags */
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#define TW_CL_REQ_RETRY_ON_BUSY (1<<0)
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#define TW_CL_REQ_CALLBACK_FOR_SGLIST (1<<1)
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#define TW_CL_MESSAGE_SOURCE_CONTROLLER_ERROR 3
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#define TW_CL_MESSAGE_SOURCE_CONTROLLER_EVENT 4
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#define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR 21
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#define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT 22
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#define TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER 5
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#define TW_CL_MESSAGE_SOURCE_FREEBSD_OS 8
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#define TW_CL_MESSAGE_SOURCE_WINDOWS_DRIVER 7
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#define TW_CL_MESSAGE_SOURCE_WINDOWS_OS 10
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#define TW_CL_SEVERITY_ERROR 0x1
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#define TW_CL_SEVERITY_WARNING 0x2
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#define TW_CL_SEVERITY_INFO 0x3
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#define TW_CL_SEVERITY_DEBUG 0x4
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#define TW_CL_SEVERITY_ERROR_STRING "ERROR"
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#define TW_CL_SEVERITY_WARNING_STRING "WARNING"
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#define TW_CL_SEVERITY_INFO_STRING "INFO"
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#define TW_CL_SEVERITY_DEBUG_STRING "DEBUG"
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/*
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* Structure, a pointer to which is used as the controller handle in
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* communications between the OS Layer and the Common Layer.
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*/
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struct tw_cl_ctlr_handle {
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TW_VOID *osl_ctlr_ctxt; /* OSL's ctlr context */
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TW_VOID *cl_ctlr_ctxt; /* CL's ctlr context */
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};
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/*
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* Structure, a pointer to which is used as the request handle in
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* communications between the OS Layer and the Common Layer.
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*/
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struct tw_cl_req_handle {
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TW_VOID *osl_req_ctxt; /* OSL's request context */
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TW_VOID *cl_req_ctxt; /* CL's request context */
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TW_UINT8 is_io; /* Only freeze/release simq for IOs */
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};
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/* Structure used to describe SCSI requests to CL. */
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struct tw_cl_scsi_req_packet {
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TW_UINT32 unit; /* unit # to send cmd to */
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TW_UINT32 lun; /* LUN to send cmd to */
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TW_UINT8 *cdb; /* ptr to SCSI cdb */
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TW_UINT32 cdb_len; /* # of valid cdb bytes */
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TW_UINT32 sense_len; /* # of bytes of valid sense info */
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TW_UINT8 *sense_data; /* ptr to sense data, if any */
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TW_UINT32 scsi_status; /* SCSI status returned by fw */
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TW_UINT32 sgl_entries; /* # of SG descriptors */
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TW_UINT8 *sg_list; /* ptr to SG list */
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};
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/* Structure used to describe pass through command packets to CL. */
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struct tw_cl_passthru_req_packet {
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TW_UINT8 *cmd_pkt; /* ptr to passthru cmd pkt */
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TW_UINT32 cmd_pkt_length; /* size of cmd pkt */
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TW_UINT32 sgl_entries; /* # of SG descriptors */
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TW_UINT8 *sg_list; /* ptr to SG list */
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};
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/* Request packet submitted to the Common Layer, by the OS Layer. */
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struct tw_cl_req_packet {
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TW_UINT32 cmd; /* Common Layer cmd */
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TW_UINT32 flags; /* flags describing request */
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TW_UINT32 status; /* Common Layer returned status */
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TW_VOID (*tw_osl_callback)(struct tw_cl_req_handle *req_handle);
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/* OSL routine to be called by CL on req completion */
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TW_VOID (*tw_osl_sgl_callback)(
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struct tw_cl_req_handle *req_handle, TW_VOID *sg_list,
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TW_UINT32 *num_sgl_entries);
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/* OSL callback to get SG list. */
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union {
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struct tw_cl_scsi_req_packet scsi_req; /* SCSI req */
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struct tw_cl_passthru_req_packet pt_req;/*Passthru req*/
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} gen_req_pkt;
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};
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#pragma pack(1)
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/*
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* Packet that describes an AEN/error generated by the controller,
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* Common Layer, or even the OS Layer.
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*/
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struct tw_cl_event_packet {
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TW_UINT32 sequence_id;
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TW_UINT32 time_stamp_sec;
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TW_UINT16 aen_code;
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TW_UINT8 severity;
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TW_UINT8 retrieved;
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TW_UINT8 repeat_count;
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TW_UINT8 parameter_len;
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TW_UINT8 parameter_data[98];
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TW_UINT32 event_src;
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TW_UINT8 severity_str[20];
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};
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#pragma pack()
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/* Structure to link 2 adjacent elements in a list. */
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struct tw_cl_link {
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struct tw_cl_link *next;
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struct tw_cl_link *prev;
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};
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#pragma pack(1)
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/* Scatter/Gather list entry with 32 bit addresses. */
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struct tw_cl_sg_desc32 {
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TW_UINT32 address;
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TW_UINT32 length;
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};
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/* Scatter/Gather list entry with 64 bit addresses. */
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struct tw_cl_sg_desc64 {
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TW_UINT64 address;
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TW_UINT32 length;
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};
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#pragma pack()
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/* Byte swap functions. Valid only if running on big endian platforms. */
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#ifdef TW_OSL_BIG_ENDIAN
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#define TW_CL_SWAP16_WITH_CAST(x) \
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((x << 8) | (x >> 8))
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#define TW_CL_SWAP32_WITH_CAST(x) \
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((x << 24) | ((x << 8) & (0xFF0000)) | \
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((x >> 8) & (0xFF00)) | (x >> 24))
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#define TW_CL_SWAP64_WITH_CAST(x) \
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((((TW_UINT64)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[1]))) << 32) |\
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((TW_UINT32)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[0]))))
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#else /* TW_OSL_BIG_ENDIAN */
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#define TW_CL_SWAP16_WITH_CAST(x) x
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#define TW_CL_SWAP32_WITH_CAST(x) x
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#define TW_CL_SWAP64_WITH_CAST(x) x
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#endif /* TW_OSL_BIG_ENDIAN */
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#define TW_CL_SWAP16(x) TW_CL_SWAP16_WITH_CAST((TW_UINT16)(x))
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#define TW_CL_SWAP32(x) TW_CL_SWAP32_WITH_CAST((TW_UINT32)(x))
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#define TW_CL_SWAP64(x) TW_CL_SWAP64_WITH_CAST((TW_UINT64)(x))
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/* Queue manipulation functions. */
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/* Initialize a queue. */
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#define TW_CL_Q_INIT(head) do { \
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(head)->prev = (head)->next = head; \
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} while (0)
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/* Insert an item at the head of the queue. */
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#define TW_CL_Q_INSERT_HEAD(head, item) do { \
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(item)->next = (head)->next; \
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(item)->prev = head; \
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(head)->next->prev = item; \
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(head)->next = item; \
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} while (0)
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/* Insert an item at the tail of the queue. */
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#define TW_CL_Q_INSERT_TAIL(head, item) do { \
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(item)->next = head; \
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(item)->prev = (head)->prev; \
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(head)->prev->next = item; \
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(head)->prev = item; \
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} while (0)
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/* Remove an item from the head of the queue. */
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#define TW_CL_Q_REMOVE_ITEM(head, item) do { \
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(item)->prev->next = (item)->next; \
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(item)->next->prev = (item)->prev; \
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} while (0)
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/* Retrieve the item at the head of the queue. */
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#define TW_CL_Q_FIRST_ITEM(head) \
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(((head)->next != head) ? ((head)->next) : TW_CL_NULL)
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/* Retrieve the item at the tail of the queue. */
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#define TW_CL_Q_LAST_ITEM(head) \
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(((head)->prev != head) ? ((head)->prev) : TW_CL_NULL)
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/* Retrieve the item next to a given item in the queue. */
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#define TW_CL_Q_NEXT_ITEM(head, item) \
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(((item)->next != head) ? ((item)->next) : TW_CL_NULL)
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/* Retrieve the item previous to a given item in the queue. */
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#define TW_CL_Q_PREV_ITEM(head, item) \
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(((item)->prev != head) ? ((item)->prev) : TW_CL_NULL)
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/* Determine the offset of a field from the head of the structure it is in. */
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#define TW_CL_STRUCT_OFFSET(struct_type, field) \
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(TW_INT8 *)(&((struct_type *)0)->field)
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/*
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* Determine the address of the head of a structure, given the address of a
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* field within it.
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*/
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#define TW_CL_STRUCT_HEAD(addr, struct_type, field) \
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(struct_type *)((TW_INT8 *)addr - \
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TW_CL_STRUCT_OFFSET(struct_type, field))
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#ifndef TW_BUILDING_API
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#include "tw_osl_inline.h"
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/*
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* The following are extern declarations of OS Layer defined functions called
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* by the Common Layer. If any function has been defined as a macro in
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* tw_osl_share.h, we will not make the extern declaration here.
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*/
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#ifndef tw_osl_breakpoint
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/* Allows setting breakpoints in the CL code for debugging purposes. */
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extern TW_VOID tw_osl_breakpoint(TW_VOID);
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#endif
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#ifndef tw_osl_timeout
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/* Start OS timeout() routine after controller reset sequence */
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extern TW_VOID tw_osl_timeout(struct tw_cl_req_handle *req_handle);
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#endif
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#ifndef tw_osl_untimeout
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/* Stop OS timeout() routine during controller reset sequence */
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extern TW_VOID tw_osl_untimeout(struct tw_cl_req_handle *req_handle);
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#endif
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#ifndef tw_osl_cur_func
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/* Text name of current function. */
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extern TW_INT8 *tw_osl_cur_func(TW_VOID);
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#endif
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#ifdef TW_OSL_DEBUG
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#ifndef tw_osl_dbg_printf
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/* Print to syslog/event log/debug console, as applicable. */
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extern TW_INT32 tw_osl_dbg_printf(struct tw_cl_ctlr_handle *ctlr_handle,
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const TW_INT8 *fmt, ...);
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#endif
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#endif /* TW_OSL_DEBUG */
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#ifndef tw_osl_delay
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/* Cause a delay of usecs micro-seconds. */
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extern TW_VOID tw_osl_delay(TW_INT32 usecs);
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#endif
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#ifndef tw_osl_destroy_lock
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/* Create/initialize a lock for CL's use. */
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extern TW_VOID tw_osl_destroy_lock(struct tw_cl_ctlr_handle *ctlr_handle,
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TW_LOCK_HANDLE *lock);
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#endif
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#ifndef tw_osl_free_lock
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/* Free a previously held lock. */
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extern TW_VOID tw_osl_free_lock(struct tw_cl_ctlr_handle *ctlr_handle,
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TW_LOCK_HANDLE *lock);
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#endif
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#ifndef tw_osl_get_local_time
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/* Get local time. */
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extern TW_TIME tw_osl_get_local_time(TW_VOID);
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#endif
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#ifndef tw_osl_get_lock
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/* Acquire a lock. */
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extern TW_VOID tw_osl_get_lock(struct tw_cl_ctlr_handle *ctlr_handle,
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TW_LOCK_HANDLE *lock);
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#endif
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#ifndef tw_osl_init_lock
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/* Create/initialize a lock for CL's use. */
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extern TW_VOID tw_osl_init_lock(struct tw_cl_ctlr_handle *ctlr_handle,
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TW_INT8 *lock_name, TW_LOCK_HANDLE *lock);
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#endif
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#ifndef tw_osl_memcpy
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/* Copy 'size' bytes from 'src' to 'dest'. */
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extern TW_VOID tw_osl_memcpy(TW_VOID *src, TW_VOID *dest, TW_INT32 size);
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#endif
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#ifndef tw_osl_memzero
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/* Zero 'size' bytes starting at 'addr'. */
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extern TW_VOID tw_osl_memzero(TW_VOID *addr, TW_INT32 size);
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#endif
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#ifndef tw_osl_notify_event
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/* Notify OSL of a controller/CL (or even OSL) event. */
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extern TW_VOID tw_osl_notify_event(struct tw_cl_ctlr_handle *ctlr_handle,
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struct tw_cl_event_packet *event);
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#endif
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#ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE
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#ifndef tw_osl_read_pci_config
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/* Read 'size' bytes from 'offset' in the PCI config space. */
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extern TW_UINT32 tw_osl_read_pci_config(
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struct tw_cl_ctlr_handle *ctlr_handle, TW_INT32 offset, TW_INT32 size);
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#endif
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#endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */
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#ifndef tw_osl_read_reg
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/* Read 'size' bytes at 'offset' from base address of this controller. */
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extern TW_UINT32 tw_osl_read_reg(struct tw_cl_ctlr_handle *ctlr_handle,
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TW_INT32 offset, TW_INT32 size);
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#endif
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#ifndef tw_osl_scan_bus
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/* Request OSL for a bus scan. */
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extern TW_VOID tw_osl_scan_bus(struct tw_cl_ctlr_handle *ctlr_handle);
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#endif
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#ifdef TW_OSL_CAN_SLEEP
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#ifndef tw_osl_sleep
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/* Sleep for 'timeout' ms or until woken up (by tw_osl_wakeup). */
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extern TW_INT32 tw_osl_sleep(struct tw_cl_ctlr_handle *ctlr_handle,
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TW_SLEEP_HANDLE *sleep_handle, TW_INT32 timeout);
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#endif
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#endif /* TW_OSL_CAN_SLEEP */
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#ifndef tw_osl_sprintf
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/* Standard sprintf. */
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extern TW_INT32 tw_osl_sprintf(TW_INT8 *dest, const TW_INT8 *fmt, ...);
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#endif
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#ifndef tw_osl_strcpy
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/* Copy string 'src' to 'dest'. */
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extern TW_INT8 *tw_osl_strcpy(TW_INT8 *dest, TW_INT8 *src);
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#endif
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#ifndef tw_osl_strlen
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/* Return length of string pointed at by 'str'. */
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extern TW_INT32 tw_osl_strlen(TW_VOID *str);
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#endif
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#ifndef tw_osl_vsprintf
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/* Standard vsprintf. */
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extern TW_INT32 tw_osl_vsprintf(TW_INT8 *dest, const TW_INT8 *fmt, va_list ap);
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#endif
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#ifdef TW_OSL_CAN_SLEEP
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#ifndef tw_osl_wakeup
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/* Wake up a thread sleeping by a call to tw_osl_sleep. */
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extern TW_VOID tw_osl_wakeup(struct tw_cl_ctlr_handle *ctlr_handle,
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TW_SLEEP_HANDLE *sleep_handle);
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#endif
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#endif /* TW_OSL_CAN_SLEEP */
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#ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE
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#ifndef tw_osl_write_pci_config
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/* Write 'value' of 'size' bytes at 'offset' in the PCI config space. */
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extern TW_VOID tw_osl_write_pci_config(struct tw_cl_ctlr_handle *ctlr_handle,
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TW_INT32 offset, TW_INT32 value, TW_INT32 size);
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#endif
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#endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */
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#ifndef tw_osl_write_reg
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/*
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* Write 'value' of 'size' (max 4) bytes at 'offset' from base address of
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* this controller.
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*/
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extern TW_VOID tw_osl_write_reg(struct tw_cl_ctlr_handle *ctlr_handle,
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TW_INT32 offset, TW_INT32 value, TW_INT32 size);
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#endif
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/* Functions in the Common Layer */
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/* Creates and queues AEN's. Also notifies OS Layer. */
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extern TW_VOID tw_cl_create_event(struct tw_cl_ctlr_handle *ctlr_handle,
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TW_UINT8 queue_event, TW_UINT8 event_src, TW_UINT16 event_code,
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TW_UINT8 severity, TW_UINT8 *severity_str, TW_UINT8 *event_desc,
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TW_UINT8 *event_specific_desc, ...);
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|
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/* Indicates whether a ctlr is supported by CL. */
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extern TW_INT32 tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id);
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/* Submit a firmware cmd packet. */
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extern TW_INT32 tw_cl_fw_passthru(struct tw_cl_ctlr_handle *ctlr_handle,
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struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle);
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/* Find out how much memory CL needs. */
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extern TW_INT32 tw_cl_get_mem_requirements(
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struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
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TW_INT32 device_id, TW_INT32 max_simult_reqs, TW_INT32 max_aens,
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TW_UINT32 *alignment, TW_UINT32 *sg_size_factor,
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TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size
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);
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/* Return PCI BAR info. */
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extern TW_INT32 tw_cl_get_pci_bar_info(TW_INT32 device_id, TW_INT32 bar_type,
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TW_INT32 *bar_num, TW_INT32 *bar0_offset, TW_INT32 *bar_size);
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|
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/* Initialize Common Layer for a given controller. */
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extern TW_INT32 tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle,
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TW_UINT32 flags, TW_INT32 device_id, TW_INT32 max_simult_reqs,
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TW_INT32 max_aens, TW_VOID *non_dma_mem, TW_VOID *dma_mem,
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|
TW_UINT64 dma_mem_phys
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|
);
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|
|
|
extern TW_VOID tw_cl_set_reset_needed(struct tw_cl_ctlr_handle *ctlr_handle);
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|
extern TW_INT32 tw_cl_is_reset_needed(struct tw_cl_ctlr_handle *ctlr_handle);
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|
extern TW_INT32 tw_cl_is_active(struct tw_cl_ctlr_handle *ctlr_handle);
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|
/* CL's interrupt handler. */
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|
extern TW_INT32 tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle);
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|
|
|
/* CL's ioctl handler. */
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|
extern TW_INT32 tw_cl_ioctl(struct tw_cl_ctlr_handle *ctlr_handle,
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|
u_long cmd, TW_VOID *buf);
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|
|
|
#ifdef TW_OSL_DEBUG
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|
/* Print CL's state/statistics for a controller. */
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|
extern TW_VOID tw_cl_print_ctlr_stats(struct tw_cl_ctlr_handle *ctlr_handle);
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|
|
|
/* Prints CL internal details of a given request. */
|
|
extern TW_VOID tw_cl_print_req_info(struct tw_cl_req_handle *req_handle);
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|
#endif /* TW_OSL_DEBUG */
|
|
|
|
/* Soft reset controller. */
|
|
extern TW_INT32 tw_cl_reset_ctlr(struct tw_cl_ctlr_handle *ctlr_handle);
|
|
|
|
#ifdef TW_OSL_DEBUG
|
|
/* Reset CL's statistics for a controller. */
|
|
extern TW_VOID tw_cl_reset_stats(struct tw_cl_ctlr_handle *ctlr_handle);
|
|
#endif /* TW_OSL_DEBUG */
|
|
|
|
/* Stop a controller. */
|
|
extern TW_INT32 tw_cl_shutdown_ctlr(struct tw_cl_ctlr_handle *ctlr_handle,
|
|
TW_UINT32 flags);
|
|
|
|
/* Submit a SCSI I/O request. */
|
|
extern TW_INT32 tw_cl_start_io(struct tw_cl_ctlr_handle *ctlr_handle,
|
|
struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle);
|
|
|
|
#endif /* TW_BUILDING_API */
|
|
|
|
#endif /* TW_CL_SHARE_H */
|