190 lines
7.8 KiB
C
190 lines
7.8 KiB
C
/*-
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* Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __AR934X_REG_H__
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#define __AR934X_REG_H__
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#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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#define AR934X_GMAC_SIZE 0x14
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#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR934X_WMAC_SIZE 0x20000
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#define AR934X_EHCI_BASE 0x1b000000
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#define AR934X_EHCI_SIZE 0x200
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#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
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#define AR934X_SRIF_SIZE 0x1000
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/* AR934x GMAC configuration */
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#define AR934X_GMAC_REG_ETH_CFG (AR934X_GMAC_BASE + 0x00)
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#define AR934X_ETH_CFG_RGMII_GMAC0 (1 << 0)
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#define AR934X_ETH_CFG_MII_GMAC0 (1 << 1)
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#define AR934X_ETH_CFG_GMII_GMAC0 (1 << 2)
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#define AR934X_ETH_CFG_MII_GMAC0_MASTER (1 << 3)
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#define AR934X_ETH_CFG_MII_GMAC0_SLAVE (1 << 4)
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#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN (1 << 5)
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#define AR934X_ETH_CFG_SW_ONLY_MODE (1 << 6)
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#define AR934X_ETH_CFG_SW_PHY_SWAP (1 << 7)
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#define AR934X_ETH_CFG_SW_APB_ACCESS (1 << 9)
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#define AR934X_ETH_CFG_RMII_GMAC0 (1 << 10)
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#define AR933X_ETH_CFG_MII_CNTL_SPEED (1 << 11)
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#define AR934X_ETH_CFG_RMII_GMAC0_MASTER (1 << 12)
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#define AR934X_ETH_CFG_SW_ACC_MSB_FIRST (1 << 13)
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#define AR934X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c)
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#define AR934X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0)
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#define AR934X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4)
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#define AR934X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8)
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#define AR934X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac)
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#define AR934X_PLL_CPU_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x00)
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#define AR934X_PLL_DDR_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x04)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08)
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#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x24)
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#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL (1 << 6)
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#define AR934X_PLL_ETH_XMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x2c)
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#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
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#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
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#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
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#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
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#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
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#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
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#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
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#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
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#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
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#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
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#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
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#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
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#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS (1 << 2)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS (1 << 3)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS (1 << 4)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL (1 << 20)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL (1 << 21)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL (1 << 24)
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#define AR934X_RESET_REG_RESET_MODULE (AR71XX_RST_BLOCK_BASE + 0x1c)
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#define AR934X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xb0)
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#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS (AR71XX_RST_BLOCK_BASE + 0xac)
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#define AR934X_RESET_GE1_MDIO (1 << 23)
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#define AR934X_RESET_GE0_MDIO (1 << 22)
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#define AR934X_RESET_GE1_MAC (1 << 13)
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#define AR934X_RESET_ETH_SWITCH_ANALOG (1 << 12)
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#define AR934X_RESET_USB_PHY_ANALOG (1 << 11)
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#define AR934X_RESET_GE0_MAC (1 << 9)
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#define AR934X_RESET_ETH_SWITCH (1 << 8)
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#define AR934X_RESET_USB_HOST (1 << 5)
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#define AR934X_RESET_USB_PHY (1 << 4)
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#define AR934X_RESET_USBSUS_OVERRIDE (1 << 3)
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#define AR934X_BOOTSTRAP_SW_OPTION8 (1 << 23)
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#define AR934X_BOOTSTRAP_SW_OPTION7 (1 << 22)
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#define AR934X_BOOTSTRAP_SW_OPTION6 (1 << 21)
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#define AR934X_BOOTSTRAP_SW_OPTION5 (1 << 20)
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#define AR934X_BOOTSTRAP_SW_OPTION4 (1 << 19)
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#define AR934X_BOOTSTRAP_SW_OPTION3 (1 << 18)
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#define AR934X_BOOTSTRAP_SW_OPTION2 (1 << 17)
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#define AR934X_BOOTSTRAP_SW_OPTION1 (1 << 16)
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#define AR934X_BOOTSTRAP_USB_MODE_DEVICE (1 << 7)
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#define AR934X_BOOTSTRAP_PCIE_RC (1 << 6)
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#define AR934X_BOOTSTRAP_EJTAG_MODE (1 << 5)
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#define AR934X_BOOTSTRAP_REF_CLK_40 (1 << 4)
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#define AR934X_BOOTSTRAP_BOOT_FROM_SPI (1 << 2)
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#define AR934X_BOOTSTRAP_SDRAM_DISABLED (1 << 1)
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#define AR934X_BOOTSTRAP_DDR1 (1 << 0)
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#define AR934X_PCIE_WMAC_INT_WMAC_MISC (1 << 0)
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#define AR934X_PCIE_WMAC_INT_WMAC_TX (1 << 1)
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#define AR934X_PCIE_WMAC_INT_WMAC_RXLP (1 << 2)
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#define AR934X_PCIE_WMAC_INT_WMAC_RXHP (1 << 3)
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#define AR934X_PCIE_WMAC_INT_PCIE_RC (1 << 4)
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#define AR934X_PCIE_WMAC_INT_PCIE_RC0 (1 << 5)
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#define AR934X_PCIE_WMAC_INT_PCIE_RC1 (1 << 6)
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#define AR934X_PCIE_WMAC_INT_PCIE_RC2 (1 << 7)
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#define AR934X_PCIE_WMAC_INT_PCIE_RC3 (1 << 8)
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#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
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(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
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AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
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#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
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(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
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AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
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AR934X_PCIE_WMAC_INT_PCIE_RC3)
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#define REV_ID_MAJOR_AR9341 0x0120
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#define REV_ID_MAJOR_AR9342 0x1120
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#define REV_ID_MAJOR_AR9344 0x2120
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#define AR934X_REV_ID_REVISION_MASK 0xf
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/*
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* GPIO block
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*/
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#define AR934X_GPIO_REG_FUNC 0x6c
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#define AR934X_GPIO_COUNT 23
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/*
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* SRIF block
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*/
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#define AR934X_SRIF_CPU_DPLL1_REG (AR934X_SRIF_BASE + 0x1c0)
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#define AR934X_SRIF_CPU_DPLL2_REG (AR934X_SRIF_BASE + 0x1c4)
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#define AR934X_SRIF_CPU_DPLL3_REG (AR934X_SRIF_BASE + 0x1c8)
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#define AR934X_SRIF_DDR_DPLL1_REG (AR934X_SRIF_BASE + 0x240)
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#define AR934X_SRIF_DDR_DPLL2_REG (AR934X_SRIF_BASE + 0x244)
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#define AR934X_SRIF_DDR_DPLL3_REG (AR934X_SRIF_BASE + 0x248)
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#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
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#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
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#define AR934X_SRIF_DPLL1_NINT_SHIFT 18
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#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
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#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
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#define AR934X_SRIF_DPLL2_LOCAL_PLL (1 << 30)
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#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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/* XXX verify! */
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#define AR934X_PLL_VAL_1000 0x16000000
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#define AR934X_PLL_VAL_100 0x00000101
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#define AR934X_PLL_VAL_10 0x00001616
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#endif /* __AR934X_REG_H__ */
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