56248d9da8
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
163 lines
5.3 KiB
C
163 lines
5.3 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Module to support operations on core such as TLB config, etc.
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*
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* <hr>$Revision: 70030 $<hr>
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*
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*/
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#include <linux/module.h>
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#include <asm/octeon/cvmx.h>
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#include <asm/octeon/cvmx-core.h>
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#else
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#include "cvmx-config.h"
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#include "cvmx.h"
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#include "cvmx-core.h"
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#endif
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/**
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* Adds a wired TLB entry, and returns the index of the entry added.
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* Parameters are written to TLB registers without further processing.
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*
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* @param hi HI register value
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* @param lo0 lo0 register value
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* @param lo1 lo1 register value
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* @param page_mask pagemask register value
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*
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* @return Success: TLB index used (0-31 Octeon, 0-63 Octeon+, or 0-127
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* Octeon2). Failure: -1
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*/
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int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask)
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{
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uint32_t index;
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CVMX_MF_TLB_WIRED(index);
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if (index >= (unsigned int)cvmx_core_get_tlb_entries())
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{
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return(-1);
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}
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CVMX_MT_ENTRY_HIGH(hi);
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CVMX_MT_ENTRY_LO_0(lo0);
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CVMX_MT_ENTRY_LO_1(lo1);
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CVMX_MT_PAGEMASK(page_mask);
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CVMX_MT_TLB_INDEX(index);
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CVMX_MT_TLB_WIRED(index + 1);
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CVMX_EHB;
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CVMX_TLBWI;
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CVMX_EHB;
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return(index);
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}
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/**
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* Adds a fixed (wired) TLB mapping. Returns TLB index used or -1 on error.
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* This is a wrapper around cvmx_core_add_wired_tlb_entry()
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*
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* @param vaddr Virtual address to map
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* @param page0_addr page 0 physical address, with low 3 bits representing the DIRTY, VALID, and GLOBAL bits
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* @param page1_addr page1 physical address, with low 3 bits representing the DIRTY, VALID, and GLOBAL bits
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* @param page_mask page mask.
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*
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* @return Success: TLB index used (0-31)
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* Failure: -1
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*/
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int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask)
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{
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if ((vaddr & (page_mask | 0x7ff))
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|| ((page0_addr & ~0x7ULL) & ((page_mask | 0x7ff) >> 1))
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|| ((page1_addr & ~0x7ULL) & ((page_mask | 0x7ff) >> 1)))
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{
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cvmx_dprintf("Error adding tlb mapping: invalid address alignment at vaddr: 0x%llx\n", (unsigned long long)vaddr);
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return(-1);
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}
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return(cvmx_core_add_wired_tlb_entry(vaddr,
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(page0_addr >> 6) | (page0_addr & 0x7),
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(page1_addr >> 6) | (page1_addr & 0x7),
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page_mask));
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}
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/**
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* Adds a fixed (wired) TLB mapping. Returns TLB index used or -1 on error.
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* Assumes both pages are valid. Use cvmx_core_add_fixed_tlb_mapping_bits for more control.
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* This is a wrapper around cvmx_core_add_wired_tlb_entry()
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*
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* @param vaddr Virtual address to map
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* @param page0_addr page 0 physical address
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* @param page1_addr page1 physical address
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* @param page_mask page mask.
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*
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* @return Success: TLB index used (0-31)
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* Failure: -1
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*/
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int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask)
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{
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return(cvmx_core_add_fixed_tlb_mapping_bits(vaddr, page0_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page1_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page_mask));
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}
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/**
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* Return number of TLB entries.
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*/
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int cvmx_core_get_tlb_entries(void)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
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return 32;
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else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
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return 64;
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else
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return 128;
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}
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