41341ca726
bus interface does that's special here now is to use a 64-bit register size. In theory, uart(4) ought to support a regsz as well as regshft and support 64-bit registers directly. Also use the UART class's range rather than a hand-coded 1024 for the address range.
834 lines
21 KiB
C
834 lines
21 KiB
C
/*-
|
|
* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
|
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* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
*
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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|
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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|
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/*
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* uart_dev_oct16550.c
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*
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* Derived from uart_dev_ns8250.c
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*
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* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
*
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*
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|
*/
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|
|
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <machine/bus.h>
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#include <machine/pcpu.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/ic/ns16550.h>
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#include <mips/cavium/octeon_pcmap_regs.h>
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#include <contrib/octeon-sdk/cvmx.h>
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#include <contrib/octeon-sdk/cvmx-interrupt.h>
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#include "uart_if.h"
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|
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/*
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* Clear pending interrupts. THRE is cleared by reading IIR. Data
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* that may have been received gets lost here.
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*/
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static void
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oct16550_clrint (struct uart_bas *bas)
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{
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uint8_t iir;
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iir = uart_getreg(bas, REG_IIR);
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while ((iir & IIR_NOPEND) == 0) {
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iir &= IIR_IMASK;
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if (iir == IIR_RLS)
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(void)uart_getreg(bas, REG_LSR);
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else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
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(void)uart_getreg(bas, REG_DATA);
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else if (iir == IIR_MLSC)
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(void)uart_getreg(bas, REG_MSR);
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else if (iir == IIR_BUSY)
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(void) uart_getreg(bas, REG_USR);
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uart_barrier(bas);
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iir = uart_getreg(bas, REG_IIR);
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}
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}
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static int delay_changed = 1;
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static int
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oct16550_delay (struct uart_bas *bas)
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{
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int divisor;
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u_char lcr;
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static int delay = 0;
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if (!delay_changed) return delay;
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delay_changed = 0;
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lcr = uart_getreg(bas, REG_LCR);
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uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
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uart_barrier(bas);
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divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
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uart_barrier(bas);
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uart_setreg(bas, REG_LCR, lcr);
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uart_barrier(bas);
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if(!bas->rclk)
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return 10; /* return an approx delay value */
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/* 1/10th the time to transmit 1 character (estimate). */
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if (divisor <= 134)
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return (16000000 * divisor / bas->rclk);
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return (16000 * divisor / (bas->rclk / 1000));
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}
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static int
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oct16550_divisor (int rclk, int baudrate)
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{
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int actual_baud, divisor;
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int error;
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if (baudrate == 0)
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return (0);
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divisor = (rclk / (baudrate << 3) + 1) >> 1;
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if (divisor == 0 || divisor >= 65536)
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return (0);
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actual_baud = rclk / (divisor << 4);
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/* 10 times error in percent: */
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error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
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/* 3.0% maximum error tolerance: */
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if (error < -30 || error > 30)
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return (0);
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return (divisor);
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}
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static int
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oct16550_drain (struct uart_bas *bas, int what)
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{
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int delay, limit;
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delay = oct16550_delay(bas);
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if (what & UART_DRAIN_TRANSMITTER) {
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/*
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* Pick an arbitrary high limit to avoid getting stuck in
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* an infinite loop when the hardware is broken. Make the
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* limit high enough to handle large FIFOs.
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*/
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limit = 10*10*10*1024;
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while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
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DELAY(delay);
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if (limit == 0) {
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/* printf("oct16550: transmitter appears stuck... "); */
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return (0);
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}
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}
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if (what & UART_DRAIN_RECEIVER) {
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/*
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* Pick an arbitrary high limit to avoid getting stuck in
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* an infinite loop when the hardware is broken. Make the
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* limit high enough to handle large FIFOs and integrated
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* UARTs. The HP rx2600 for example has 3 UARTs on the
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* management board that tend to get a lot of data send
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* to it when the UART is first activated.
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*/
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limit=10*4096;
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while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
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(void)uart_getreg(bas, REG_DATA);
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uart_barrier(bas);
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DELAY(delay << 2);
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}
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if (limit == 0) {
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/* printf("oct16550: receiver appears broken... "); */
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return (EIO);
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}
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}
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return (0);
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}
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/*
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* We can only flush UARTs with FIFOs. UARTs without FIFOs should be
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* drained. WARNING: this function clobbers the FIFO setting!
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*/
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static void
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oct16550_flush (struct uart_bas *bas, int what)
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{
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uint8_t fcr;
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fcr = FCR_ENABLE;
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if (what & UART_FLUSH_TRANSMITTER)
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fcr |= FCR_XMT_RST;
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if (what & UART_FLUSH_RECEIVER)
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fcr |= FCR_RCV_RST;
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uart_setreg(bas, REG_FCR, fcr);
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uart_barrier(bas);
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}
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static int
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oct16550_param (struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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int divisor;
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uint8_t lcr;
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lcr = 0;
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if (databits >= 8)
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lcr |= LCR_8BITS;
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else if (databits == 7)
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lcr |= LCR_7BITS;
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else if (databits == 6)
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lcr |= LCR_6BITS;
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else
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lcr |= LCR_5BITS;
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if (stopbits > 1)
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lcr |= LCR_STOPB;
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lcr |= parity << 3;
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/* Set baudrate. */
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if (baudrate > 0) {
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divisor = oct16550_divisor(bas->rclk, baudrate);
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if (divisor == 0)
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return (EINVAL);
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uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
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uart_barrier(bas);
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uart_setreg(bas, REG_DLL, divisor & 0xff);
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uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
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uart_barrier(bas);
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delay_changed = 1;
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}
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/* Set LCR and clear DLAB. */
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uart_setreg(bas, REG_LCR, lcr);
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uart_barrier(bas);
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return (0);
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}
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/*
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* Low-level UART interface.
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*/
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static int oct16550_probe(struct uart_bas *bas);
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static void oct16550_init(struct uart_bas *bas, int, int, int, int);
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static void oct16550_term(struct uart_bas *bas);
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static void oct16550_putc(struct uart_bas *bas, int);
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static int oct16550_rxready(struct uart_bas *bas);
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static int oct16550_getc(struct uart_bas *bas, struct mtx *);
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struct uart_ops uart_oct16550_ops = {
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.probe = oct16550_probe,
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.init = oct16550_init,
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.term = oct16550_term,
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.putc = oct16550_putc,
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.rxready = oct16550_rxready,
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.getc = oct16550_getc,
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};
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static int
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oct16550_probe (struct uart_bas *bas)
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{
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u_char val;
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/* Check known 0 bits that don't depend on DLAB. */
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val = uart_getreg(bas, REG_IIR);
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if (val & 0x30)
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return (ENXIO);
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val = uart_getreg(bas, REG_MCR);
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if (val & 0xc0)
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return (ENXIO);
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val = uart_getreg(bas, REG_USR);
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if (val & 0xe0)
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return (ENXIO);
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return (0);
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}
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static void
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oct16550_init (struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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u_char ier;
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oct16550_param(bas, baudrate, databits, stopbits, parity);
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|
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/* Disable all interrupt sources. */
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ier = uart_getreg(bas, REG_IER) & 0x0;
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uart_setreg(bas, REG_IER, ier);
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uart_barrier(bas);
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|
|
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/* Disable the FIFO (if present). */
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// uart_setreg(bas, REG_FCR, 0);
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uart_barrier(bas);
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|
|
|
/* Set RTS & DTR. */
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uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR);
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uart_barrier(bas);
|
|
|
|
oct16550_clrint(bas);
|
|
}
|
|
|
|
static void
|
|
oct16550_term (struct uart_bas *bas)
|
|
{
|
|
|
|
/* Clear RTS & DTR. */
|
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uart_setreg(bas, REG_MCR, 0);
|
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uart_barrier(bas);
|
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}
|
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|
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static inline void oct16550_wait_txhr_empty (struct uart_bas *bas, int limit, int delay)
|
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{
|
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while (((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) &&
|
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((uart_getreg(bas, REG_USR) & USR_TXFIFO_NOTFULL) == 0))
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DELAY(delay);
|
|
}
|
|
|
|
static void
|
|
oct16550_putc (struct uart_bas *bas, int c)
|
|
{
|
|
int delay;
|
|
|
|
/* 1/10th the time to transmit 1 character (estimate). */
|
|
delay = oct16550_delay(bas);
|
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oct16550_wait_txhr_empty(bas, 100, delay);
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uart_setreg(bas, REG_DATA, c);
|
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uart_barrier(bas);
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oct16550_wait_txhr_empty(bas, 100, delay);
|
|
}
|
|
|
|
static int
|
|
oct16550_rxready (struct uart_bas *bas)
|
|
{
|
|
|
|
return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
|
|
}
|
|
|
|
static int
|
|
oct16550_getc (struct uart_bas *bas, struct mtx *hwmtx)
|
|
{
|
|
int c, delay;
|
|
|
|
uart_lock(hwmtx);
|
|
|
|
/* 1/10th the time to transmit 1 character (estimate). */
|
|
delay = oct16550_delay(bas);
|
|
|
|
while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
|
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uart_unlock(hwmtx);
|
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DELAY(delay);
|
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uart_lock(hwmtx);
|
|
}
|
|
|
|
c = uart_getreg(bas, REG_DATA);
|
|
|
|
uart_unlock(hwmtx);
|
|
|
|
return (c);
|
|
}
|
|
|
|
/*
|
|
* High-level UART interface.
|
|
*/
|
|
struct oct16550_softc {
|
|
struct uart_softc base;
|
|
uint8_t fcr;
|
|
uint8_t ier;
|
|
uint8_t mcr;
|
|
};
|
|
|
|
static int oct16550_bus_attach(struct uart_softc *);
|
|
static int oct16550_bus_detach(struct uart_softc *);
|
|
static int oct16550_bus_flush(struct uart_softc *, int);
|
|
static int oct16550_bus_getsig(struct uart_softc *);
|
|
static int oct16550_bus_ioctl(struct uart_softc *, int, intptr_t);
|
|
static int oct16550_bus_ipend(struct uart_softc *);
|
|
static int oct16550_bus_param(struct uart_softc *, int, int, int, int);
|
|
static int oct16550_bus_probe(struct uart_softc *);
|
|
static int oct16550_bus_receive(struct uart_softc *);
|
|
static int oct16550_bus_setsig(struct uart_softc *, int);
|
|
static int oct16550_bus_transmit(struct uart_softc *);
|
|
|
|
static kobj_method_t oct16550_methods[] = {
|
|
KOBJMETHOD(uart_attach, oct16550_bus_attach),
|
|
KOBJMETHOD(uart_detach, oct16550_bus_detach),
|
|
KOBJMETHOD(uart_flush, oct16550_bus_flush),
|
|
KOBJMETHOD(uart_getsig, oct16550_bus_getsig),
|
|
KOBJMETHOD(uart_ioctl, oct16550_bus_ioctl),
|
|
KOBJMETHOD(uart_ipend, oct16550_bus_ipend),
|
|
KOBJMETHOD(uart_param, oct16550_bus_param),
|
|
KOBJMETHOD(uart_probe, oct16550_bus_probe),
|
|
KOBJMETHOD(uart_receive, oct16550_bus_receive),
|
|
KOBJMETHOD(uart_setsig, oct16550_bus_setsig),
|
|
KOBJMETHOD(uart_transmit, oct16550_bus_transmit),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
struct uart_class uart_oct16550_class = {
|
|
"oct16550 class",
|
|
oct16550_methods,
|
|
sizeof(struct oct16550_softc),
|
|
.uc_ops = &uart_oct16550_ops,
|
|
.uc_range = 8 << 3,
|
|
.uc_rclk = 0
|
|
};
|
|
|
|
#define SIGCHG(c, i, s, d) \
|
|
if (c) { \
|
|
i |= (i & s) ? s : s | d; \
|
|
} else { \
|
|
i = (i & s) ? (i & ~s) | d : i; \
|
|
}
|
|
|
|
static int
|
|
oct16550_bus_attach (struct uart_softc *sc)
|
|
{
|
|
struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
|
|
struct uart_bas *bas;
|
|
int unit;
|
|
|
|
unit = device_get_unit(sc->sc_dev);
|
|
bas = &sc->sc_bas;
|
|
|
|
oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
|
|
oct16550->mcr = uart_getreg(bas, REG_MCR);
|
|
oct16550->fcr = FCR_ENABLE | FCR_RX_HIGH;
|
|
uart_setreg(bas, REG_FCR, oct16550->fcr);
|
|
uart_barrier(bas);
|
|
oct16550_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
|
|
|
|
if (oct16550->mcr & MCR_DTR)
|
|
sc->sc_hwsig |= SER_DTR;
|
|
if (oct16550->mcr & MCR_RTS)
|
|
sc->sc_hwsig |= SER_RTS;
|
|
oct16550_bus_getsig(sc);
|
|
|
|
oct16550_clrint(bas);
|
|
oct16550->ier = uart_getreg(bas, REG_IER) & 0xf0;
|
|
oct16550->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY;
|
|
uart_setreg(bas, REG_IER, oct16550->ier);
|
|
uart_barrier(bas);
|
|
|
|
/*
|
|
* Enable the interrupt in CIU. // UART-x2 @ IP2
|
|
*/
|
|
switch (unit) {
|
|
case 0:
|
|
cvmx_interrupt_unmask_irq(CVMX_IRQ_UART0);
|
|
break;
|
|
case 1:
|
|
cvmx_interrupt_unmask_irq(CVMX_IRQ_UART1);
|
|
break;
|
|
default:
|
|
panic("%s: invalid UART %d", __func__, unit);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
oct16550_bus_detach (struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
u_char ier;
|
|
|
|
bas = &sc->sc_bas;
|
|
ier = uart_getreg(bas, REG_IER) & 0xf0;
|
|
uart_setreg(bas, REG_IER, ier);
|
|
uart_barrier(bas);
|
|
oct16550_clrint(bas);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
oct16550_bus_flush (struct uart_softc *sc, int what)
|
|
{
|
|
struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
|
|
struct uart_bas *bas;
|
|
int error;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
if (sc->sc_rxfifosz > 1) {
|
|
oct16550_flush(bas, what);
|
|
uart_setreg(bas, REG_FCR, oct16550->fcr);
|
|
uart_barrier(bas);
|
|
error = 0;
|
|
} else
|
|
error = oct16550_drain(bas, what);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
oct16550_bus_getsig (struct uart_softc *sc)
|
|
{
|
|
uint32_t new, old, sig;
|
|
uint8_t msr;
|
|
|
|
do {
|
|
old = sc->sc_hwsig;
|
|
sig = old;
|
|
uart_lock(sc->sc_hwmtx);
|
|
msr = uart_getreg(&sc->sc_bas, REG_MSR);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
|
|
SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
|
|
SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
|
|
SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
|
|
new = sig & ~SER_MASK_DELTA;
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
return (sig);
|
|
}
|
|
|
|
static int
|
|
oct16550_bus_ioctl (struct uart_softc *sc, int request, intptr_t data)
|
|
{
|
|
struct uart_bas *bas;
|
|
int baudrate, divisor, error;
|
|
uint8_t efr, lcr;
|
|
|
|
bas = &sc->sc_bas;
|
|
error = 0;
|
|
uart_lock(sc->sc_hwmtx);
|
|
switch (request) {
|
|
case UART_IOCTL_BREAK:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
if (data)
|
|
lcr |= LCR_SBREAK;
|
|
else
|
|
lcr &= ~LCR_SBREAK;
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
break;
|
|
case UART_IOCTL_IFLOW:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, 0xbf);
|
|
uart_barrier(bas);
|
|
efr = uart_getreg(bas, REG_EFR);
|
|
if (data)
|
|
efr |= EFR_RTS;
|
|
else
|
|
efr &= ~EFR_RTS;
|
|
uart_setreg(bas, REG_EFR, efr);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
break;
|
|
case UART_IOCTL_OFLOW:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, 0xbf);
|
|
uart_barrier(bas);
|
|
efr = uart_getreg(bas, REG_EFR);
|
|
if (data)
|
|
efr |= EFR_CTS;
|
|
else
|
|
efr &= ~EFR_CTS;
|
|
uart_setreg(bas, REG_EFR, efr);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
break;
|
|
case UART_IOCTL_BAUD:
|
|
lcr = uart_getreg(bas, REG_LCR);
|
|
uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
|
|
uart_barrier(bas);
|
|
divisor = uart_getreg(bas, REG_DLL) |
|
|
(uart_getreg(bas, REG_DLH) << 8);
|
|
uart_barrier(bas);
|
|
uart_setreg(bas, REG_LCR, lcr);
|
|
uart_barrier(bas);
|
|
baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
|
|
delay_changed = 1;
|
|
if (baudrate > 0)
|
|
*(int*)data = baudrate;
|
|
else
|
|
error = ENXIO;
|
|
break;
|
|
default:
|
|
error = EINVAL;
|
|
break;
|
|
}
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
|
|
static int
|
|
oct16550_bus_ipend(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int ipend = 0;
|
|
uint8_t iir, lsr;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
iir = uart_getreg(bas, REG_IIR) & IIR_IMASK;
|
|
if (iir != IIR_NOPEND) {
|
|
|
|
if (iir == IIR_RLS) {
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
if (lsr & LSR_OE)
|
|
ipend |= SER_INT_OVERRUN;
|
|
if (lsr & LSR_BI)
|
|
ipend |= SER_INT_BREAK;
|
|
if (lsr & LSR_RXRDY)
|
|
ipend |= SER_INT_RXREADY;
|
|
|
|
} else if (iir == IIR_RXRDY) {
|
|
ipend |= SER_INT_RXREADY;
|
|
|
|
} else if (iir == IIR_RXTOUT) {
|
|
ipend |= SER_INT_RXREADY;
|
|
|
|
} else if (iir == IIR_TXRDY) {
|
|
ipend |= SER_INT_TXIDLE;
|
|
|
|
} else if (iir == IIR_MLSC) {
|
|
ipend |= SER_INT_SIGCHG;
|
|
|
|
} else if (iir == IIR_BUSY) {
|
|
(void) uart_getreg(bas, REG_USR);
|
|
}
|
|
}
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
//#define OCTEON_VISUAL_UART 1
|
|
#ifdef OCTEON_VISUAL_UART
|
|
static int where1 = 0;
|
|
|
|
if (ipend) octeon_led_run_wheel(&where1, 6 + device_get_unit(sc->sc_dev));
|
|
#endif
|
|
|
|
return (ipend);
|
|
}
|
|
|
|
static int
|
|
oct16550_bus_param (struct uart_softc *sc, int baudrate, int databits,
|
|
int stopbits, int parity)
|
|
{
|
|
struct uart_bas *bas;
|
|
int error;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
error = oct16550_param(bas, baudrate, databits, stopbits, parity);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
oct16550_bus_probe (struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int error;
|
|
|
|
bas = &sc->sc_bas;
|
|
bas->rclk = uart_oct16550_class.uc_rclk = cvmx_sysinfo_get()->cpu_clock_hz;
|
|
|
|
error = oct16550_probe(bas);
|
|
if (error) {
|
|
return (error);
|
|
}
|
|
|
|
uart_setreg(bas, REG_MCR, (MCR_DTR | MCR_RTS));
|
|
|
|
/*
|
|
* Enable FIFOs. And check that the UART has them. If not, we're
|
|
* done. Since this is the first time we enable the FIFOs, we reset
|
|
* them.
|
|
*/
|
|
oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
|
|
#define ENABLE_OCTEON_FIFO 1
|
|
#ifdef ENABLE_OCTEON_FIFO
|
|
uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
|
|
#endif
|
|
uart_barrier(bas);
|
|
|
|
oct16550_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
|
|
|
|
if (device_get_unit(sc->sc_dev)) {
|
|
device_set_desc(sc->sc_dev, "Octeon-16550 channel 1");
|
|
} else {
|
|
device_set_desc(sc->sc_dev, "Octeon-16550 channel 0");
|
|
}
|
|
#ifdef ENABLE_OCTEON_FIFO
|
|
sc->sc_rxfifosz = 64;
|
|
sc->sc_txfifosz = 64;
|
|
#else
|
|
sc->sc_rxfifosz = 1;
|
|
sc->sc_txfifosz = 1;
|
|
#endif
|
|
|
|
|
|
#if 0
|
|
/*
|
|
* XXX there are some issues related to hardware flow control and
|
|
* it's likely that uart(4) is the cause. This basicly needs more
|
|
* investigation, but we avoid using for hardware flow control
|
|
* until then.
|
|
*/
|
|
/* 16650s or higher have automatic flow control. */
|
|
if (sc->sc_rxfifosz > 16) {
|
|
sc->sc_hwiflow = 1;
|
|
sc->sc_hwoflow = 1;
|
|
}
|
|
#endif
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
oct16550_bus_receive (struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int xc;
|
|
uint8_t lsr;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
|
|
while (lsr & LSR_RXRDY) {
|
|
if (uart_rx_full(sc)) {
|
|
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
|
break;
|
|
}
|
|
xc = uart_getreg(bas, REG_DATA);
|
|
if (lsr & LSR_FE)
|
|
xc |= UART_STAT_FRAMERR;
|
|
if (lsr & LSR_PE)
|
|
xc |= UART_STAT_PARERR;
|
|
uart_rx_put(sc, xc);
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
}
|
|
/* Discard everything left in the Rx FIFO. */
|
|
/*
|
|
* First do a dummy read/discard anyway, in case the UART was lying to us.
|
|
* This problem was seen on board, when IIR said RBR, but LSR said no RXRDY
|
|
* Results in a stuck ipend loop.
|
|
*/
|
|
(void)uart_getreg(bas, REG_DATA);
|
|
while (lsr & LSR_RXRDY) {
|
|
(void)uart_getreg(bas, REG_DATA);
|
|
uart_barrier(bas);
|
|
lsr = uart_getreg(bas, REG_LSR);
|
|
}
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
oct16550_bus_setsig (struct uart_softc *sc, int sig)
|
|
{
|
|
struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
|
|
struct uart_bas *bas;
|
|
uint32_t new, old;
|
|
|
|
bas = &sc->sc_bas;
|
|
do {
|
|
old = sc->sc_hwsig;
|
|
new = old;
|
|
if (sig & SER_DDTR) {
|
|
SIGCHG(sig & SER_DTR, new, SER_DTR,
|
|
SER_DDTR);
|
|
}
|
|
if (sig & SER_DRTS) {
|
|
SIGCHG(sig & SER_RTS, new, SER_RTS,
|
|
SER_DRTS);
|
|
}
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
uart_lock(sc->sc_hwmtx);
|
|
oct16550->mcr &= ~(MCR_DTR|MCR_RTS);
|
|
if (new & SER_DTR)
|
|
oct16550->mcr |= MCR_DTR;
|
|
if (new & SER_RTS)
|
|
oct16550->mcr |= MCR_RTS;
|
|
uart_setreg(bas, REG_MCR, oct16550->mcr);
|
|
uart_barrier(bas);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
oct16550_bus_transmit (struct uart_softc *sc)
|
|
{
|
|
struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
|
|
struct uart_bas *bas;
|
|
int i;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
#ifdef NO_UART_INTERRUPTS
|
|
for (i = 0; i < sc->sc_txdatasz; i++) {
|
|
oct16550_putc(bas, sc->sc_txbuf[i]);
|
|
}
|
|
#else
|
|
|
|
oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas));
|
|
uart_setreg(bas, REG_IER, oct16550->ier | IER_ETXRDY);
|
|
uart_barrier(bas);
|
|
|
|
for (i = 0; i < sc->sc_txdatasz; i++) {
|
|
uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
|
|
uart_barrier(bas);
|
|
}
|
|
sc->sc_txbusy = 1;
|
|
#endif
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|