131 lines
4.5 KiB
C++
131 lines
4.5 KiB
C++
/*
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* \file trc_idec_arminst.h
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* \brief OpenCSD :
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*
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* \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
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*/
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/*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef ARM_TRC_IDEC_ARMINST_H_INCLUDED
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#define ARM_TRC_IDEC_ARMINST_H_INCLUDED
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#ifndef __STDC_CONSTANT_MACROS
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#define __STDC_CONSTANT_MACROS 1
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#endif
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#include "opencsd/ocsd_if_types.h"
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#include <cstdint>
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/*
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For Thumb2, test if a halfword is the first half of a 32-bit instruction,
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as opposed to a complete 16-bit instruction.
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*/
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inline int is_wide_thumb(uint16_t insthw)
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{
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return (insthw & 0xF800) >= 0xE800;
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}
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/*
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In the following queries, 16-bit Thumb2 instructions should be
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passed in as the high halfword, e.g. xxxx0000.
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*/
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/*
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Test whether an instruction is a branch (software change of the PC).
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This includes branch instructions and all loads and data-processing
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instructions that write to the PC. It does not include exception
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instructions such as SVC, HVC and SMC.
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(Performance event 0x0C includes these.)
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*/
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int inst_ARM_is_branch(uint32_t inst);
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int inst_Thumb_is_branch(uint32_t inst);
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int inst_A64_is_branch(uint32_t inst);
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/*
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Test whether an instruction is a direct (aka immediate) branch.
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Performance event 0x0D counts these.
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*/
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int inst_ARM_is_direct_branch(uint32_t inst);
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int inst_Thumb_is_direct_branch(uint32_t inst);
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int inst_A64_is_direct_branch(uint32_t inst);
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/*
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Get branch destination for a direct branch.
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*/
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int inst_ARM_branch_destination(uint32_t addr, uint32_t inst, uint32_t *pnpc);
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int inst_Thumb_branch_destination(uint32_t addr, uint32_t inst, uint32_t *pnpc);
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int inst_A64_branch_destination(uint64_t addr, uint32_t inst, uint64_t *pnpc);
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int inst_ARM_is_indirect_branch(uint32_t inst);
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int inst_Thumb_is_indirect_branch(uint32_t inst);
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int inst_A64_is_indirect_branch(uint32_t inst);
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int inst_ARM_is_branch_and_link(uint32_t inst);
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int inst_Thumb_is_branch_and_link(uint32_t inst);
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int inst_A64_is_branch_and_link(uint32_t inst);
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int inst_ARM_is_conditional(uint32_t inst);
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int inst_Thumb_is_conditional(uint32_t inst);
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int inst_A64_is_conditional(uint32_t inst);
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/* For an IT instruction, return the number of instructions conditionalized
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(from 1 to 4). For other instructions, return zero. */
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unsigned int inst_Thumb_is_IT(uint32_t inst);
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typedef enum {
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ARM_BARRIER_NONE,
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ARM_BARRIER_ISB,
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ARM_BARRIER_DMB,
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ARM_BARRIER_DSB
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} arm_barrier_t;
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arm_barrier_t inst_ARM_barrier(uint32_t inst);
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arm_barrier_t inst_Thumb_barrier(uint32_t inst);
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arm_barrier_t inst_A64_barrier(uint32_t inst);
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/*
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Test whether an instruction is definitely undefined, e.g. because
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allocated to a "permanently UNDEFINED" space (UDF mnemonic).
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Other instructions besides the ones indicated, may always or
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sometimes cause an undefined instruction trap. This call is
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intended to be helpful in 'runaway decode' prevention.
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*/
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int inst_ARM_is_UDF(uint32_t inst);
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int inst_Thumb_is_UDF(uint32_t inst);
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int inst_A64_is_UDF(uint32_t inst);
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/* access sub-type information */
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ocsd_instr_subtype get_instr_subtype();
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void clear_instr_subtype();
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#endif // ARM_TRC_IDEC_ARMINST_H_INCLUDED
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/* End of File trc_idec_arminst.h */
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