705581e102
aic7xxx.c: Correct code that traverses the phase table. A much too quick push to staticize this structure resulted in non-functional lookup code. This corrects the printing of the phase where a timeout occurred. aic7xxx.reg: Use FIFOQWDEMP as the name for bit 5 of DFSTATUS just like the Adaptec data books. aic7xxx.seq: Refine the 2.1 PCI retry bug workaround for certain, non-ULTRA2, controllers. When the DMA of an SCB completes, it can take some time for HDONE to come true after MREQPEN (PCI memory request pending) falls. If HDONE never comes true, we are in the hung state and must manually drain the FIFO. We used to test HDONE for 3 clock cycles to detect this condition. This works on all of the hardware I can personally test. Some controllers were reported to take 4 clock cycles, so the last version of this code waited 4 clock cycles. This still didn't work for everyone. To fix this, I've adjusted the work around so that even if the hardware hasn't hung, but we run the work-around code, the result is a long winded way to complete the transfer, rather than a hang.
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