dfa1a4fbf9
signalled when the attribute address for the CF is 0 in the octeon sysinfo structure. In this mode, the DATA port is 16-bits, but the other ports are 8-bits, but on a 16-bit bus (so you have to access it a short at a time, but only believe the lower byte). See the code for more details on this slightly odd arrangement. I'm still not 100% happy with the abstractions here on many levels (starting with the globals for these settings, on down to no bus_space use, etc), but the driver had these problems before the change. Also, clean up the code a bit to make this support easier, and the code a bit easier to read. I tried to follow existing style, but may have missed a few spots. Add some comments. Fix probe/attach routine to return a proper error for the simulator. With this change, my EBH5200 eval board now recognizes the CF well enough to boot to the login prompt. Before it would say it never became ready. My CN3010-EVB-HS5 still boots properly. My older CN3860-based board won't load the 64-bit kernel, either before or after the change, and I didn't chase that down.
762 lines
21 KiB
C
762 lines
21 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/*
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* octeon_ebt3000_cf.c
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bio.h>
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#include <sys/systm.h>
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#include <sys/sysctl.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/power.h>
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#include <sys/smp.h>
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#include <sys/time.h>
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#include <sys/timetc.h>
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#include <sys/malloc.h>
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#include <geom/geom.h>
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#include <machine/clock.h>
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#include <machine/locore.h>
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#include <machine/md_var.h>
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#include <machine/cpuregs.h>
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#include <mips/cavium/octeon_pcmap_regs.h>
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#include <contrib/octeon-sdk/cvmx.h>
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/* ATA Commands */
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#define CMD_READ_SECTOR 0x20
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#define CMD_WRITE_SECTOR 0x30
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#define CMD_IDENTIFY 0xEC
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/* The ATA Task File */
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#define TF_DATA 0x00
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#define TF_ERROR 0x01
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#define TF_PRECOMP 0x01
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#define TF_SECTOR_COUNT 0x02
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#define TF_SECTOR_NUMBER 0x03
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#define TF_CYL_LSB 0x04
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#define TF_CYL_MSB 0x05
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#define TF_DRV_HEAD 0x06
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#define TF_STATUS 0x07
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#define TF_COMMAND 0x07
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/* Status Register */
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#define STATUS_BSY 0x80 /* Drive is busy */
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#define STATUS_RDY 0x40 /* Drive is ready */
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#define STATUS_DF 0x20 /* Device fault */
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#define STATUS_DRQ 0x08 /* Data can be transferred */
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/* Miscelaneous */
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#define SECTOR_SIZE 512
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#define WAIT_DELAY 1000
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#define NR_TRIES 1000
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#define SWAP_SHORT(x) ((x << 8) | (x >> 8))
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#define MODEL_STR_SIZE 40
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/* XXX */
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extern cvmx_bootinfo_t *octeon_bootinfo;
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/* Globals */
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/*
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* There's three bus types supported by this driver.
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*
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* CF_8 -- Traditional PC Card IDE interface on an 8-bit wide bus. We assume
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* the bool loader has configure attribute memory properly. We then access
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* the device like old-school 8-bit IDE card (which is all a traditional PC Card
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* interface really is).
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* CF_16 -- Traditional PC Card IDE interface on a 16-bit wide bus. Registers on
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* this bus are 16-bits wide too. When accessing registers in the task file, you
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* have to do it in 16-bit chunks, and worry about masking out what you don't want
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* or ORing together the traditional 8-bit values. We assume the bootloader does
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* the right attribute memory initialization dance.
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* CF_TRUE_IDE_8 - CF Card wired to True IDE mode. There's no Attribute memory
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* space at all. Instead all the traditional 8-bit registers are there, but
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* on a 16-bit bus where addr0 isn't wired. This means we need to read/write them
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* 16-bit chunks, but only the lower 8 bits are valid. We do not (and can not)
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* access this like CF_16 with the comingled registers. Yet we can't access
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* this like CF_8 because of the register offset. Except the TF_DATA register
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* appears to be full width?
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*/
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void *base_addr;
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int bus_type;
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#define CF_8 1 /* 8-bit bus, no offsets - PC Card */
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#define CF_16 2 /* 16-bit bus, registers shared - PC Card */
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#define CF_TRUE_IDE_8 3 /* 16-bit bus, only lower 8-bits, TrueIDE */
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const char *const cf_type[] = {
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"impossible type",
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"CF 8-bit",
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"CF 16-bit",
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"True IDE"
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};
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/* Device softc */
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struct cf_priv {
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device_t dev;
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struct drive_param *drive_param;
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struct bio_queue_head cf_bq;
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struct g_geom *cf_geom;
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struct g_provider *cf_provider;
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};
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/* Device parameters */
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struct drive_param{
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union {
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char buf[SECTOR_SIZE];
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struct ata_params driveid;
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} u;
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char model[MODEL_STR_SIZE];
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uint32_t nr_sectors;
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uint16_t sector_size;
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uint16_t heads;
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uint16_t tracks;
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uint16_t sec_track;
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} drive_param;
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/* GEOM class implementation */
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static g_access_t cf_access;
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static g_start_t cf_start;
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static g_ioctl_t cf_ioctl;
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struct g_class g_cf_class = {
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.name = "CF",
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.version = G_VERSION,
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.start = cf_start,
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.access = cf_access,
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.ioctl = cf_ioctl,
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};
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DECLARE_GEOM_CLASS(g_cf_class, g_cf);
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/* Device methods */
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static int cf_probe(device_t);
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static void cf_identify(driver_t *, device_t);
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static int cf_attach(device_t);
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static int cf_attach_geom(void *, int);
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/* ATA methods */
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static int cf_cmd_identify(void);
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static int cf_cmd_write(uint32_t, uint32_t, void *);
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static int cf_cmd_read(uint32_t, uint32_t, void *);
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static int cf_wait_busy(void);
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static int cf_send_cmd(uint32_t, uint8_t);
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static void cf_attach_geom_proxy(void *arg, int flag);
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/* Miscelenous */
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static void cf_swap_ascii(unsigned char[], char[]);
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/* ------------------------------------------------------------------- *
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* cf_access() *
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* ------------------------------------------------------------------- */
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static int cf_access (struct g_provider *pp, int r, int w, int e)
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{
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pp->sectorsize = drive_param.sector_size;
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pp->stripesize = drive_param.heads * drive_param.sec_track * drive_param.sector_size;
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pp->mediasize = pp->stripesize * drive_param.tracks;
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return (0);
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}
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/* ------------------------------------------------------------------- *
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* cf_start() *
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* ------------------------------------------------------------------- */
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static void cf_start (struct bio *bp)
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{
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int error;
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/*
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* Handle actual I/O requests. The request is passed down through
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* the bio struct.
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*/
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if(bp->bio_cmd & BIO_GETATTR) {
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if (g_handleattr_int(bp, "GEOM::fwsectors", drive_param.sec_track))
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return;
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if (g_handleattr_int(bp, "GEOM::fwheads", drive_param.heads))
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return;
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g_io_deliver(bp, ENOIOCTL);
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return;
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}
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if ((bp->bio_cmd & (BIO_READ | BIO_WRITE))) {
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if (bp->bio_cmd & BIO_READ) {
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error = cf_cmd_read(bp->bio_length / drive_param.sector_size,
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bp->bio_offset / drive_param.sector_size, bp->bio_data);
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} else if (bp->bio_cmd & BIO_WRITE) {
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error = cf_cmd_write(bp->bio_length / drive_param.sector_size,
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bp->bio_offset/drive_param.sector_size, bp->bio_data);
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} else {
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printf("%s: unrecognized bio_cmd %x.\n", __func__, bp->bio_cmd);
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error = ENOTSUP;
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}
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if (error != 0) {
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g_io_deliver(bp, error);
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return;
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}
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bp->bio_resid = 0;
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bp->bio_completed = bp->bio_length;
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g_io_deliver(bp, 0);
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}
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}
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static int cf_ioctl (struct g_provider *pp, u_long cmd, void *data, int fflag, struct thread *td)
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{
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return (0);
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}
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static uint8_t cf_inb_8(int port)
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{
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/*
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* Traditional 8-bit PC Card/CF bus access.
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*/
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if (bus_type == CF_8) {
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volatile uint8_t *task_file = (volatile uint8_t *)base_addr;
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return task_file[port];
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}
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/*
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* True IDE access. lower 8 bits on a 16-bit bus (see above).
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*/
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volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
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return task_file[port] & 0xff;
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}
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static void cf_outb_8(int port, uint8_t val)
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{
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/*
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* Traditional 8-bit PC Card/CF bus access.
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*/
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if (bus_type == CF_8) {
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volatile uint8_t *task_file = (volatile uint8_t *)base_addr;
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task_file[port] = val;
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}
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/*
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* True IDE access. lower 8 bits on a 16-bit bus (see above).
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*/
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volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
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task_file[port] = val & 0xff;
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}
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static uint8_t cf_inb_16(int port)
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{
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volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
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uint16_t val = task_file[port / 2];
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if (port & 1)
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return (val >> 8) & 0xff;
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return val & 0xff;
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}
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static uint16_t cf_inw_16(int port)
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{
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volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
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uint16_t val = task_file[port / 2];
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return val;
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}
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static void cf_outw_16(int port, uint16_t val)
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{
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volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
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task_file[port / 2] = val;
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}
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/* ------------------------------------------------------------------- *
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* cf_cmd_read() *
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* ------------------------------------------------------------------- *
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*
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* Read nr_sectors from the device starting from start_sector.
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*/
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static int cf_cmd_read (uint32_t nr_sectors, uint32_t start_sector, void *buf)
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{
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unsigned long lba;
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uint32_t count;
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uint16_t *ptr_16;
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uint8_t *ptr_8;
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int error;
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//#define OCTEON_VISUAL_CF_0 1
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#ifdef OCTEON_VISUAL_CF_0
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octeon_led_write_char(0, 'R');
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#endif
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ptr_8 = (uint8_t*)buf;
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ptr_16 = (uint16_t*)buf;
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lba = start_sector;
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while (nr_sectors--) {
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error = cf_send_cmd(lba, CMD_READ_SECTOR);
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if (error != 0) {
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printf("%s: cf_send_cmd(CMD_READ_SECTOR) failed: %d\n", __func__, error);
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return (error);
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}
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switch (bus_type)
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{
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case CF_8:
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for (count = 0; count < SECTOR_SIZE; count++) {
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*ptr_8++ = cf_inb_8(TF_DATA);
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if ((count & 0xf) == 0)
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(void)cf_inb_8(TF_STATUS);
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}
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break;
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case CF_TRUE_IDE_8:
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case CF_16:
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default:
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for (count = 0; count < SECTOR_SIZE; count+=2) {
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uint16_t temp;
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temp = cf_inw_16(TF_DATA);
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*ptr_16++ = SWAP_SHORT(temp);
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if ((count & 0xf) == 0)
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(void)cf_inb_16(TF_STATUS);
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}
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break;
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}
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lba++;
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}
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#ifdef OCTEON_VISUAL_CF_0
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octeon_led_write_char(0, ' ');
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#endif
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return (0);
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}
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/* ------------------------------------------------------------------- *
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* cf_cmd_write() *
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* ------------------------------------------------------------------- *
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*
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* Write nr_sectors to the device starting from start_sector.
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*/
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static int cf_cmd_write (uint32_t nr_sectors, uint32_t start_sector, void *buf)
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{
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uint32_t lba;
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uint32_t count;
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uint16_t *ptr_16;
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uint8_t *ptr_8;
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int error;
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//#define OCTEON_VISUAL_CF_1 1
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#ifdef OCTEON_VISUAL_CF_1
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octeon_led_write_char(1, 'W');
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#endif
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lba = start_sector;
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ptr_8 = (uint8_t*)buf;
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ptr_16 = (uint16_t*)buf;
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while (nr_sectors--) {
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error = cf_send_cmd(lba, CMD_WRITE_SECTOR);
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if (error != 0) {
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printf("%s: cf_send_cmd(CMD_WRITE_SECTOR) failed: %d\n", __func__, error);
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return (error);
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}
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switch (bus_type)
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{
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case CF_8:
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for (count = 0; count < SECTOR_SIZE; count++) {
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cf_outb_8(TF_DATA, *ptr_8++);
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if ((count & 0xf) == 0)
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(void)cf_inb_8(TF_STATUS);
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}
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break;
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case CF_TRUE_IDE_8:
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case CF_16:
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default:
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for (count = 0; count < SECTOR_SIZE; count+=2) {
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uint16_t temp = *ptr_16++;
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cf_outw_16(TF_DATA, SWAP_SHORT(temp));
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if ((count & 0xf) == 0)
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(void)cf_inb_16(TF_STATUS);
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}
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break;
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}
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lba++;
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}
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#ifdef OCTEON_VISUAL_CF_1
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octeon_led_write_char(1, ' ');
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#endif
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return (0);
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}
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/* ------------------------------------------------------------------- *
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* cf_cmd_identify() *
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* ------------------------------------------------------------------- *
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*
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* Read parameters and other information from the drive and store
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* it in the drive_param structure
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*
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*/
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static int cf_cmd_identify (void)
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{
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int count;
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int error;
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error = cf_send_cmd(0, CMD_IDENTIFY);
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if (error != 0) {
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printf("%s: identify failed: %d\n", __func__, error);
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return (error);
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}
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switch (bus_type)
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{
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case CF_8:
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for (count = 0; count < SECTOR_SIZE; count++)
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drive_param.u.buf[count] = cf_inb_8(TF_DATA);
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break;
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case CF_TRUE_IDE_8:
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case CF_16:
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default:
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for (count = 0; count < SECTOR_SIZE; count += 2) {
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uint16_t temp;
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temp = cf_inw_16(TF_DATA);
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/* endianess will be swapped below */
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drive_param.u.buf[count] = (temp & 0xff);
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drive_param.u.buf[count + 1] = (temp & 0xff00) >> 8;
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}
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break;
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}
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cf_swap_ascii(drive_param.u.driveid.model, drive_param.model);
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drive_param.sector_size = 512; //= SWAP_SHORT (drive_param.u.driveid.sector_bytes);
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drive_param.heads = SWAP_SHORT (drive_param.u.driveid.current_heads);
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drive_param.tracks = SWAP_SHORT (drive_param.u.driveid.current_cylinders);
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drive_param.sec_track = SWAP_SHORT (drive_param.u.driveid.current_sectors);
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drive_param.nr_sectors = (uint32_t)SWAP_SHORT (drive_param.u.driveid.lba_size_1) |
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((uint32_t)SWAP_SHORT (drive_param.u.driveid.lba_size_2));
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printf("cf0: <%s> %lld sectors\n", drive_param.model, (long long)drive_param.nr_sectors);
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return (0);
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}
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/* ------------------------------------------------------------------- *
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* cf_send_cmd() *
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|
* ------------------------------------------------------------------- *
|
|
*
|
|
* Send command to read/write one sector specified by lba.
|
|
*
|
|
*/
|
|
static int cf_send_cmd (uint32_t lba, uint8_t cmd)
|
|
{
|
|
switch (bus_type)
|
|
{
|
|
case CF_8:
|
|
case CF_TRUE_IDE_8:
|
|
while (cf_inb_8(TF_STATUS) & STATUS_BSY)
|
|
DELAY(WAIT_DELAY);
|
|
cf_outb_8(TF_SECTOR_COUNT, 1);
|
|
cf_outb_8(TF_SECTOR_NUMBER, lba & 0xff);
|
|
cf_outb_8(TF_CYL_LSB, (lba >> 8) & 0xff);
|
|
cf_outb_8(TF_CYL_MSB, (lba >> 16) & 0xff);
|
|
cf_outb_8(TF_DRV_HEAD, ((lba >> 24) & 0xff) | 0xe0);
|
|
cf_outb_8(TF_COMMAND, cmd);
|
|
break;
|
|
case CF_16:
|
|
default:
|
|
while (cf_inb_16(TF_STATUS) & STATUS_BSY)
|
|
DELAY(WAIT_DELAY);
|
|
cf_outw_16(TF_SECTOR_COUNT, 1 | ((lba & 0xff) << 8));
|
|
cf_outw_16(TF_CYL_LSB, ((lba >> 8) & 0xff) | (((lba >> 16) & 0xff) << 8));
|
|
cf_outw_16(TF_DRV_HEAD, (((lba >> 24) & 0xff) | 0xe0) | (cmd << 8));
|
|
break;
|
|
}
|
|
|
|
return (cf_wait_busy());
|
|
}
|
|
|
|
/* ------------------------------------------------------------------- *
|
|
* cf_wait_busy() *
|
|
* ------------------------------------------------------------------- *
|
|
*
|
|
* Wait until the drive finishes a given command and data is
|
|
* ready to be transferred. This is done by repeatedly checking
|
|
* the BSY bit of the status register. When the controller is ready for
|
|
* data transfer, it clears the BSY bit and sets the DRQ bit.
|
|
*
|
|
* If the DF bit is ever set, we return error.
|
|
*
|
|
* This code originally spun on DRQ. If that behavior turns out to be
|
|
* necessary, a flag can be added or this function can be called
|
|
* repeatedly as long as it is returning ENXIO.
|
|
*/
|
|
static int cf_wait_busy (void)
|
|
{
|
|
uint8_t status;
|
|
|
|
//#define OCTEON_VISUAL_CF_2 1
|
|
#ifdef OCTEON_VISUAL_CF_2
|
|
static int where0 = 0;
|
|
|
|
octeon_led_run_wheel(&where0, 2);
|
|
#endif
|
|
|
|
switch (bus_type)
|
|
{
|
|
case CF_8:
|
|
case CF_TRUE_IDE_8:
|
|
status = cf_inb_8(TF_STATUS);
|
|
while ((status & STATUS_BSY) == STATUS_BSY) {
|
|
if ((status & STATUS_DF) != 0) {
|
|
printf("%s: device fault (status=%x)\n", __func__, status);
|
|
return (EIO);
|
|
}
|
|
DELAY(WAIT_DELAY);
|
|
status = cf_inb_8(TF_STATUS);
|
|
}
|
|
break;
|
|
case CF_16:
|
|
default:
|
|
status = cf_inb_16(TF_STATUS);
|
|
while ((status & STATUS_BSY) == STATUS_BSY) {
|
|
if ((status & STATUS_DF) != 0) {
|
|
printf("%s: device fault (status=%x)\n", __func__, status);
|
|
return (EIO);
|
|
}
|
|
DELAY(WAIT_DELAY);
|
|
status = cf_inb_16(TF_STATUS);
|
|
}
|
|
break;
|
|
}
|
|
if ((status & STATUS_DRQ) == 0) {
|
|
printf("%s: device not ready (status=%x)\n", __func__, status);
|
|
return (ENXIO);
|
|
}
|
|
|
|
#ifdef OCTEON_VISUAL_CF_2
|
|
octeon_led_write_char(2, ' ');
|
|
#endif
|
|
return (0);
|
|
}
|
|
|
|
/* ------------------------------------------------------------------- *
|
|
* cf_swap_ascii() *
|
|
* ------------------------------------------------------------------- *
|
|
*
|
|
* The ascii string returned by the controller specifying
|
|
* the model of the drive is byte-swaped. This routine
|
|
* corrects the byte ordering.
|
|
*
|
|
*/
|
|
static void cf_swap_ascii (unsigned char str1[], char str2[])
|
|
{
|
|
int i;
|
|
|
|
for(i = 0; i < MODEL_STR_SIZE; i++)
|
|
str2[i] = str1[i ^ 1];
|
|
}
|
|
|
|
|
|
/* ------------------------------------------------------------------- *
|
|
* cf_probe() *
|
|
* ------------------------------------------------------------------- */
|
|
|
|
static int cf_probe (device_t dev)
|
|
{
|
|
if (octeon_is_simulation())
|
|
return (ENXIO);
|
|
|
|
if (device_get_unit(dev) != 0) {
|
|
panic("can't attach more devices\n");
|
|
}
|
|
|
|
device_set_desc(dev, "Octeon Compact Flash Driver");
|
|
|
|
return (cf_cmd_identify());
|
|
}
|
|
|
|
/* ------------------------------------------------------------------- *
|
|
* cf_identify() *
|
|
* ------------------------------------------------------------------- *
|
|
*
|
|
* Find the bootbus region for the CF to determine
|
|
* 16 or 8 bit and check to see if device is
|
|
* inserted.
|
|
*
|
|
*/
|
|
typedef unsigned long long llu;
|
|
static void cf_identify (driver_t *drv, device_t parent)
|
|
{
|
|
int bus_region;
|
|
int count = 0;
|
|
cvmx_mio_boot_reg_cfgx_t cfg;
|
|
|
|
if (octeon_is_simulation())
|
|
return;
|
|
|
|
base_addr = cvmx_phys_to_ptr(octeon_bootinfo->compact_flash_common_base_addr);
|
|
|
|
for (bus_region = 0; bus_region < 8; bus_region++)
|
|
{
|
|
cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(bus_region));
|
|
if (cfg.s.base == octeon_bootinfo->compact_flash_common_base_addr >> 16)
|
|
{
|
|
if (octeon_bootinfo->compact_flash_attribute_base_addr == 0)
|
|
bus_type = CF_TRUE_IDE_8;
|
|
else
|
|
bus_type = (cfg.s.width) ? CF_16 : CF_8;
|
|
printf("Compact flash found in bootbus region %d (%s).\n", bus_region, cf_type[bus_type]);
|
|
break;
|
|
}
|
|
}
|
|
|
|
switch (bus_type)
|
|
{
|
|
case CF_8:
|
|
case CF_TRUE_IDE_8:
|
|
/* Check if CF is inserted */
|
|
while (cf_inb_8(TF_STATUS) & STATUS_BSY) {
|
|
if ((count++) == NR_TRIES ) {
|
|
printf("Compact Flash not present\n");
|
|
return;
|
|
}
|
|
DELAY(WAIT_DELAY);
|
|
}
|
|
break;
|
|
case CF_16:
|
|
default:
|
|
/* Check if CF is inserted */
|
|
while (cf_inb_16(TF_STATUS) & STATUS_BSY) {
|
|
if ((count++) == NR_TRIES ) {
|
|
printf("Compact Flash not present\n");
|
|
return;
|
|
}
|
|
DELAY(WAIT_DELAY);
|
|
}
|
|
break;
|
|
}
|
|
|
|
BUS_ADD_CHILD(parent, 0, "cf", 0);
|
|
}
|
|
|
|
|
|
/* ------------------------------------------------------------------- *
|
|
* cf_attach_geom() *
|
|
* ------------------------------------------------------------------- */
|
|
|
|
static int cf_attach_geom (void *arg, int flag)
|
|
{
|
|
struct cf_priv *cf_priv;
|
|
|
|
cf_priv = (struct cf_priv *) arg;
|
|
cf_priv->cf_geom = g_new_geomf(&g_cf_class, "cf%d", device_get_unit(cf_priv->dev));
|
|
cf_priv->cf_provider = g_new_providerf(cf_priv->cf_geom, cf_priv->cf_geom->name);
|
|
cf_priv->cf_geom->softc = cf_priv;
|
|
g_error_provider(cf_priv->cf_provider, 0);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/* ------------------------------------------------------------------- *
|
|
* cf_attach_geom() *
|
|
* ------------------------------------------------------------------- */
|
|
static void cf_attach_geom_proxy (void *arg, int flag)
|
|
{
|
|
cf_attach_geom(arg, flag);
|
|
}
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------------- *
|
|
* cf_attach() *
|
|
* ------------------------------------------------------------------- */
|
|
|
|
static int cf_attach (device_t dev)
|
|
{
|
|
struct cf_priv *cf_priv;
|
|
|
|
if (octeon_is_simulation())
|
|
return (ENXIO);
|
|
|
|
cf_priv = device_get_softc(dev);
|
|
cf_priv->dev = dev;
|
|
cf_priv->drive_param = &drive_param;
|
|
|
|
g_post_event(cf_attach_geom_proxy, cf_priv, M_WAITOK, NULL);
|
|
bioq_init(&cf_priv->cf_bq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static device_method_t cf_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, cf_probe),
|
|
DEVMETHOD(device_identify, cf_identify),
|
|
DEVMETHOD(device_attach, cf_attach),
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t cf_driver = {
|
|
"cf",
|
|
cf_methods,
|
|
sizeof(struct cf_priv)
|
|
};
|
|
|
|
static devclass_t cf_devclass;
|
|
|
|
DRIVER_MODULE(cf, nexus, cf_driver, cf_devclass, 0, 0);
|