293 lines
8.3 KiB
C
293 lines
8.3 KiB
C
/* $NetBSD: fpu_div.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)fpu_div.c 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Perform an FPU divide (return x / y).
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <machine/fpu.h>
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#include <machine/reg.h>
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#include <powerpc/fpu/fpu_arith.h>
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#include <powerpc/fpu/fpu_emu.h>
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/*
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* Division of normal numbers is done as follows:
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*
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* x and y are floating point numbers, i.e., in the form 1.bbbb * 2^e.
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* If X and Y are the mantissas (1.bbbb's), the quotient is then:
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*
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* q = (X / Y) * 2^((x exponent) - (y exponent))
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*
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* Since X and Y are both in [1.0,2.0), the quotient's mantissa (X / Y)
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* will be in [0.5,2.0). Moreover, it will be less than 1.0 if and only
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* if X < Y. In that case, it will have to be shifted left one bit to
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* become a normal number, and the exponent decremented. Thus, the
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* desired exponent is:
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*
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* left_shift = x->fp_mant < y->fp_mant;
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* result_exp = x->fp_exp - y->fp_exp - left_shift;
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*
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* The quotient mantissa X/Y can then be computed one bit at a time
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* using the following algorithm:
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*
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* Q = 0; -- Initial quotient.
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* R = X; -- Initial remainder,
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* if (left_shift) -- but fixed up in advance.
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* R *= 2;
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* for (bit = FP_NMANT; --bit >= 0; R *= 2) {
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* if (R >= Y) {
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* Q |= 1 << bit;
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* R -= Y;
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* }
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* }
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*
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* The subtraction R -= Y always removes the uppermost bit from R (and
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* can sometimes remove additional lower-order 1 bits); this proof is
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* left to the reader.
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*
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* This loop correctly calculates the guard and round bits since they are
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* included in the expanded internal representation. The sticky bit
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* is to be set if and only if any other bits beyond guard and round
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* would be set. From the above it is obvious that this is true if and
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* only if the remainder R is nonzero when the loop terminates.
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*
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* Examining the loop above, we can see that the quotient Q is built
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* one bit at a time ``from the top down''. This means that we can
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* dispense with the multi-word arithmetic and just build it one word
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* at a time, writing each result word when it is done.
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*
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* Furthermore, since X and Y are both in [1.0,2.0), we know that,
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* initially, R >= Y. (Recall that, if X < Y, R is set to X * 2 and
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* is therefore at in [2.0,4.0).) Thus Q is sure to have bit FP_NMANT-1
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* set, and R can be set initially to either X - Y (when X >= Y) or
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* 2X - Y (when X < Y). In addition, comparing R and Y is difficult,
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* so we will simply calculate R - Y and see if that underflows.
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* This leads to the following revised version of the algorithm:
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*
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* R = X;
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* bit = FP_1;
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* D = R - Y;
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* if (D >= 0) {
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* result_exp = x->fp_exp - y->fp_exp;
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* R = D;
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* q = bit;
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* bit >>= 1;
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* } else {
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* result_exp = x->fp_exp - y->fp_exp - 1;
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* q = 0;
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* }
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* R <<= 1;
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* do {
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* D = R - Y;
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* if (D >= 0) {
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* q |= bit;
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* R = D;
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* }
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* R <<= 1;
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* } while ((bit >>= 1) != 0);
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* Q[0] = q;
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* for (i = 1; i < 4; i++) {
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* q = 0, bit = 1 << 31;
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* do {
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* D = R - Y;
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* if (D >= 0) {
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* q |= bit;
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* R = D;
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* }
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* R <<= 1;
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* } while ((bit >>= 1) != 0);
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* Q[i] = q;
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* }
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*
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* This can be refined just a bit further by moving the `R <<= 1'
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* calculations to the front of the do-loops and eliding the first one.
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* The process can be terminated immediately whenever R becomes 0, but
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* this is relatively rare, and we do not bother.
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*/
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struct fpn *
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fpu_div(struct fpemu *fe)
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{
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struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2;
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u_int q, bit;
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u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3;
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FPU_DECL_CARRY
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/*
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* Since divide is not commutative, we cannot just use ORDER.
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* Check either operand for NaN first; if there is at least one,
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* order the signalling one (if only one) onto the right, then
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* return it. Otherwise we have the following cases:
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*
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* Inf / Inf = NaN, plus NV exception
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* Inf / num = Inf [i.e., return x]
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* Inf / 0 = Inf [i.e., return x]
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* 0 / Inf = 0 [i.e., return x]
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* 0 / num = 0 [i.e., return x]
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* 0 / 0 = NaN, plus NV exception
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* num / Inf = 0
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* num / num = num (do the divide)
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* num / 0 = Inf, plus DZ exception
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*/
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DPRINTF(FPE_REG, ("fpu_div:\n"));
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DUMPFPN(FPE_REG, x);
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DUMPFPN(FPE_REG, y);
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DPRINTF(FPE_REG, ("=>\n"));
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if (ISNAN(x) || ISNAN(y)) {
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ORDER(x, y);
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fe->fe_cx |= FPSCR_VXSNAN;
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DUMPFPN(FPE_REG, y);
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return (y);
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}
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/*
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* Need to split the following out cause they generate different
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* exceptions.
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*/
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if (ISINF(x)) {
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if (x->fp_class == y->fp_class) {
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fe->fe_cx |= FPSCR_VXIDI;
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return (fpu_newnan(fe));
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}
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DUMPFPN(FPE_REG, x);
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return (x);
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}
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if (ISZERO(x)) {
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fe->fe_cx |= FPSCR_ZX;
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if (x->fp_class == y->fp_class) {
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fe->fe_cx |= FPSCR_VXZDZ;
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return (fpu_newnan(fe));
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}
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DUMPFPN(FPE_REG, x);
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return (x);
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}
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/* all results at this point use XOR of operand signs */
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x->fp_sign ^= y->fp_sign;
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if (ISINF(y)) {
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x->fp_class = FPC_ZERO;
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DUMPFPN(FPE_REG, x);
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return (x);
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}
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if (ISZERO(y)) {
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fe->fe_cx = FPSCR_ZX;
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x->fp_class = FPC_INF;
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DUMPFPN(FPE_REG, x);
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return (x);
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}
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/*
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* Macros for the divide. See comments at top for algorithm.
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* Note that we expand R, D, and Y here.
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*/
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#define SUBTRACT /* D = R - Y */ \
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FPU_SUBS(d3, r3, y3); FPU_SUBCS(d2, r2, y2); \
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FPU_SUBCS(d1, r1, y1); FPU_SUBC(d0, r0, y0)
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#define NONNEGATIVE /* D >= 0 */ \
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((int)d0 >= 0)
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#ifdef FPU_SHL1_BY_ADD
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#define SHL1 /* R <<= 1 */ \
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FPU_ADDS(r3, r3, r3); FPU_ADDCS(r2, r2, r2); \
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FPU_ADDCS(r1, r1, r1); FPU_ADDC(r0, r0, r0)
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#else
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#define SHL1 \
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r0 = (r0 << 1) | (r1 >> 31), r1 = (r1 << 1) | (r2 >> 31), \
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r2 = (r2 << 1) | (r3 >> 31), r3 <<= 1
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#endif
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#define LOOP /* do ... while (bit >>= 1) */ \
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do { \
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SHL1; \
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SUBTRACT; \
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if (NONNEGATIVE) { \
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q |= bit; \
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r0 = d0, r1 = d1, r2 = d2, r3 = d3; \
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} \
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} while ((bit >>= 1) != 0)
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#define WORD(r, i) /* calculate r->fp_mant[i] */ \
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q = 0; \
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bit = 1 << 31; \
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LOOP; \
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(x)->fp_mant[i] = q
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/* Setup. Note that we put our result in x. */
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r0 = x->fp_mant[0];
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r1 = x->fp_mant[1];
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r2 = x->fp_mant[2];
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r3 = x->fp_mant[3];
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y0 = y->fp_mant[0];
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y1 = y->fp_mant[1];
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y2 = y->fp_mant[2];
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y3 = y->fp_mant[3];
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bit = FP_1;
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SUBTRACT;
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if (NONNEGATIVE) {
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x->fp_exp -= y->fp_exp;
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r0 = d0, r1 = d1, r2 = d2, r3 = d3;
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q = bit;
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bit >>= 1;
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} else {
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x->fp_exp -= y->fp_exp + 1;
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q = 0;
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}
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LOOP;
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x->fp_mant[0] = q;
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WORD(x, 1);
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WORD(x, 2);
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WORD(x, 3);
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x->fp_sticky = r0 | r1 | r2 | r3;
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DUMPFPN(FPE_REG, x);
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return (x);
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}
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