e5e9ae1dc2
1. At least some Netra t1 models have PCI buses with no associated interrupt map, but obviously expect the PCI swizzle to be done with the interrupt number from the higher level as intpin. In this case, the mapping also needs to continue at parent bus nodes. To handle that, add a quirk table based on the "name" property of the root node to avoid breaking other boxen. This property is now retrieved and printed at boot. 2. On SPARCengine Ultra AX machines, interrupt numbers are not mapped at all, and full interrupt numbers (not just INOs) are given in the interrupt properties. This is more or less cosmetical; the PCI interrupt numbers would be wrong, but the psycho resource allocation method would pass the right numbers on anyway. Tested by: mux (1), Maxim Mazurok <maxim@km.ua> (2)
74 lines
2.7 KiB
C
74 lines
2.7 KiB
C
/*-
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* Copyright (c) 2001 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_VER_H_
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#define _MACHINE_VER_H_
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#define VER_MANUF_SHIFT (48)
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#define VER_IMPL_SHIFT (32)
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#define VER_MASK_SHIFT (24)
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#define VER_MAXTL_SHIFT (8)
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#define VER_MAXWIN_SHIFT (0)
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#define VER_MANUF_SIZE (16)
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#define VER_IMPL_SIZE (16)
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#define VER_MASK_SIZE (8)
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#define VER_MAXTL_SIZE (8)
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#define VER_MAXWIN_SIZE (5)
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#define VER_MANUF_MASK (((1L<<VER_MANUF_SIZE)-1)<<VER_MANUF_SHIFT)
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#define VER_IMPL_MASK (((1L<<VER_IMPL_SIZE)-1)<<VER_IMPL_SHIFT)
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#define VER_MASK_MASK (((1L<<VER_MASK_SIZE)-1)<<VER_MASK_SHIFT)
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#define VER_MAXTL_MASK (((1L<<VER_MAXTL_SIZE)-1)<<VER_MAXTL_SHIFT)
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#define VER_MAXWIN_MASK (((1L<<VER_MAXWIN_SIZE)-1)<<VER_MAXWIN_SHIFT)
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#define VER_MANUF(ver) \
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(((ver) & VER_MANUF_MASK) >> VER_MANUF_SHIFT)
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#define VER_IMPL(ver) \
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(((ver) & VER_IMPL_MASK) >> VER_IMPL_SHIFT)
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#define VER_MASK(ver) \
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(((ver) & VER_MASK_MASK) >> VER_MASK_SHIFT)
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#define VER_MAXTL(ver) \
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(((ver) & VER_MAXTL_MASK) >> VER_MAXTL_SHIFT)
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#define VER_MAXWIN(ver) \
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(((ver) & VER_MAXWIN_MASK) >> VER_MAXWIN_SHIFT)
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extern int cpu_impl;
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extern char sparc64_model[];
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/* Known implementations. */
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#define CPU_IMPL_SPARC64 0x01
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#define CPU_IMPL_ULTRASPARCI 0x10
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#define CPU_IMPL_ULTRASPARCII 0x11
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#define CPU_IMPL_ULTRASPARCIIi 0x12
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#define CPU_IMPL_ULTRASPARCIIe 0x13
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#define CPU_IMPL_ULTRASPARCIII 0x14
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#define CPU_IMPL_ULTRASPARCIIIp 0x15
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#endif /* !_MACHINE_VER_H_ */
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